ارائه یک فلیپ فلاپ غیر فرار، کم مصرف و سریع مبتنی بر NCFET با قابلیت پشتیبان گیری همزمان برای محاسبات غیر فرار

نوع مقاله : علمی-پژوهشی

نویسندگان

1 دانشجوی کارشناسی ارشد، دانشکده مهندسی کامپیوتر، دانشگاه شهید باهنر کرمان، کرمان، ایران

2 استادیار، دانشکده مهندسی کامپیوتر، دانشگاه شهید باهنر کرمان، کرمان، ایران

چکیده

در مدارهای محاسباتی، قطع غیرمنتظره منبع ولتاژ باعث از دست رفتن داده ها و انجام مجدد محاسبات می شود. این امر باعث کاهش سرعت محاسبات و افزایش توان مصرفی می گردد. در نتیجه امروزه طراحی مدارهای محاسباتی با استفاده از عناصر غیرفرار بسیار مورد توجه قرار گرفته است. در این مدارها پیاده سازی تکنیک power-gating که نقش مهمی در کاهش توان نشتی ایفا می کند آسان تر و کم هزینه تر است. در مدارهای غیرفراری که تاکنون پیشنهاد شده است از یک مدار پشتیبان گیر مجزا استفاده می شود که در فاصله های زمانی مشخص، عمل ذخیره سازی حالت D-flip-flop های روی تراشه را انجام می دهد. اما استفاده از مدار پشتیبان گیر مجزا، در نهایت منجر به افزایش توان مصرفی کل، سطح اشغال شده، و کاهش سرعت محاسبات می گردد. علاوه براین، مدار پشتیبان گیر به سیگنال های کنترلی خارجی نیازمند است که پیچیدگی سیستم را افزایش می دهد. برای حل این مشکلات، در این مقاله یک فلیپ فلاپ غیر فرار جدید، با قابلیت پشتیبان گیری همزمان از داده، پیشنهاد شده است که برای پیشبرد اساسی الگوی محاسبات غیرفرار، از ترانزیستور فروالکتریک NCFET استفاده می‌کند. فلیپ فلاپ پیشنهاد شده برای عملیات پشتیبان گیری و بازیابی، انرژی در سطح fJ و تاخیری در سطح ps دارد.

کلیدواژه‌ها

موضوعات


عنوان مقاله [English]

A Non-volatile, Low-Power, and Fast NCFET-based Flip-Flop with Simultaneous Backup Capability for Non-volatile Computing

نویسندگان [English]

  • R. Abbasi 1
  • V. Jamshidi 2
1 Department of Computer Engineering, Shahid Bahonar University of Kerman (SBUK), Kerman, Iran
2 Department of Computer Engineering, Shahid Bahonar University of Kerman (SBUK), Kerman, Iran
چکیده [English]

In computing circuits, the unexpected interruption of the voltage source causes the loss of data and redoing the calculations, which reduces the speed of calculations and increases the power consumption. Consequently, today, the design of computing circuits using non-volatile elements has received much attention. In these circuits, it is easier and less expensive to implement the power-gating technique, which plays an important role in reducing leakage power. In the non-volatile circuits that have been proposed so far, a separate back-up module is used, which saves the state of the D-flip-flops on the chip at specific time intervals. However, the use of a separate backup module ultimately leads to an increase in the total power consumption, the occupied area, and a decrease in the calculation speed. In addition, the backup module requires external control signals, which increases the complexity of the system. To solve these problems, in this paper, a new non-volatile flip-flop with simultaneous data backup capability is proposed, which uses NCFET ferroelectric transistor to fundamentally advance the non-volatile computing paradigm. The proposed flip-flop for backup and recovery operation has energy at fJ level and delay at ps level.

کلیدواژه‌ها [English]

  • Data backup
  • ferroelectric transistor
  • hysteresis
  • non-volatility
  • non-volatile flip-flop
  • data restore
[1] مهسا مهراد، میثم بارعی «ارائه ساختار نوین ترانزیستور اثر میدان سیلیسیم روی عایق دو گیتی با پنجره اکسید در درین گسترده شده به منظور کاربرد در تکنولوژی نانو»، مجله مهندسی برق دانشگاه تبریز، دوره 47، شماره 2، صفحات 727 - 733 ، 1396.
[2] رامین رجایی «طراحی یک فلیپ فلاپ کم توان، پرسرعت و مصون از خطای نرم برای فن آوری های نانومتری‎»، مجله مهندسی برق دانشگاه تبریز، دوره 50، شماره 1، صفحات 137-146، 1399.
[3] Ma et al., “Architecture exploration for ambient energy harvesting nonvolatile processors,” in Proc. IEEE 21st Int. Symp. High Perform. Comput. Archit. (HPCA), Burlingame, CA, USA, pp. 526–537, Feb. 2015.
[4] Li, U. D. Heo, K. Ma, V. Narayanan, H. Liu, and S. Datta, “RF powered systems using steep-slope devices,” in Proc. IEEE 12th Int. New Circuits Syst. Conf. (NEWCAS), Trois-Rivières, QC, Canada, pp. 73–76, Jun. 2014.
[5] Kim et al., “Ambient RF energy-harvesting technologies for self sustainable standalone wireless sensor platforms,” Proc. IEEE, vol. 102, no. 11, pp. 1649–1666, Nov. 2014.
[6] Su, Y. Liu, Y. Wang, and H. Yang, “A ferroelectric nonvolatile processor with 46 μs system-level wake-up time and 14 μs sleep time for energy harvesting applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 3, pp. 596–607, Mar. 2017.
[7] Liu et al., “A 65 nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 84–86, Jan./Feb. 2016.
[8] A. Saki, S. H. Lin, M. Alam, S. K. Thirumala, S. K. Gupta, and S. Ghosh, "A family of compact non-volatile flip-flops with ferroelectric FET,'' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 11, pp. 4219 4229, Nov. 2019.
[9] Zhang et al., “Solar power prediction assisted intra-task scheduling for nonvolatile sensor nodes,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 35, no. 5, pp. 724–737, May 2016.
[10] Wang et al., “Storage-less and converter-less photovoltaic energy harvesting with maximum power point tracking for Internet of Things,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 35, no. 2, pp. 173–186, Feb. 2016.
[11] Jabeur, G. Di Pendina, F. Bernard-Granger, and G. Prenat, “Spin orbit torque non-volatile flip-flop for high speed and low energy applications,” IEEE electron device letters, vol. 35, no. 3, pp. 408–410, 2014.
[12] Wang, W. Zhao, E. Deng, Y. Zhang, and J.-O. Klein, “Magnetic non-volatile flip-flop with spin-hall assistance,” physica status solidi (RRL)–Rapid Research Letters, vol. 9, no. 6, pp. 375–378, 2015.
[13] Bishnoi, F. Oboril, and M. B. Tahoori, “Non-volatile non-shadow flip-flop using spin orbit torque for efficient normally-off computing,” in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, pp. 769–774, 2016.
[14] Seo, X. Fong, and K. Roy, “Fast and disturb-free nonvolatile flip-flop using complementary polarizer mtj,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1573–1577, 2016.
[15] Fong, Y. Kim, S. H. Choday, and K. Roy, “Failure mitigation techniques for 1t-1mtj spin-transfer torque mram bit-cells,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 384–395, 2013.
[16] Markovic D. , Nikolic B. , Brodersen R. W. "Analysis and design of low-energy flip-flops" Proceeding of International Symposium on Low Power Electronics and Design, pp. 52 -55, Aug. 2001.
[17] Li, Xueqing, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta et al. "Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 11, pp. 2907-2919, 2017.
[18] Li, Xueqing, Sumitha George, Yuhua Liang, Kaisheng Ma, Kai Ni, Ahmedullah Aziz, Sumeet Kumar Gupta et al. "Lowering area overheads for FeFET-based energy-efficient nonvolatile flip-flops." IEEE Transactions on Electron Devices, vol. 65, no. 6, pp. 2670-2674, 2018.
[19] Thirumala, Sandeep Krishna, Arnab Raha, Hrishikesh Jayakumar, Kaisheng Ma, V. Narayanan, Vijay Raghunathan, and Sumeet Kumar Gupta. "Dual mode ferroelectric transistor based non-volatile flip-flops for intermittently-powered systems." In Proceedings of the International Symposium on Low Power Electronics and Design, pp. 1-6, 2018.
[20] Mitchell, M. Hunt, C. McCartney, and F. Ho, “Implementation of low-power, non-volatile latch utilizing ferroelectric transistor,” Electronics Letters, vol. 51, no. 23, pp. 1884–1886, 2015.
[21] Zhao, E. Belhaire, V. Javerliac, C. Chappert, and B. Dieny, “A non-volatile flip-flop in magnetic fpga chip,” in International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006, pp. 323–326, 2006.
[22] Jamshidi, "NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-based look-up table for ultralow power and highly reliable FPGA designs." Turkish Journal of Electrical Engineering and Computer Sciences 27, no. 6, pp. 4486-4501, 2019.
[23] Ryu, J. Kim, J. Jung, J. P. Kim, S. H. Kang, and S.-O. Jung, “A magnetic tunnel junction based zero standby leakage current retention flip-flop,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 11, pp. 2044–2053, 2011.
[24] Lakys,W. Zhao, J.-O. Klein, and C. Chappert, “Low power, high reliability magnetic flip-flop,” Electronics letters, vol. 46, no. 22, pp. 1493–1494, 2010.
[25] Jamshidi, A. Patooghy, M. Fazeli, "MagCiM: A Flexible and Non-Volatile Computing-in-Memory Processor for Energy-Efficient Logic Computation." IEEE Access 10, pp. 35445-35459, 2022.
[26] Kimura, T. Fuchikami, K. Maramoto, Y. Fujimori, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A 2.4 pj ferroelectric-based non-volatile flip-flop with 10-year data retention capability,” in 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, pp. 21–24, 2014.
[27] Qazi, A. Amerasekera, and A. P. Chandrakasan, “A 3.4-pj FeRAM-enabled D flip-flop in 0.13um cmos for nonvolatile processing in digital systems,” IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 202–211, 2013.
[28] Izumi, H. Kawaguchi, M. Yoshimoto, H. Kimura, T. Fuchikami, K. Marumoto, and Y. Fujimori, “A ferroelectric-based non-volatile flip-flop for wearable healthcare systems,” in 2015 15th Non-Volatile Memory Technology Symposium (NVMTS). IEEE, pp.1–4, 2015.
[29] Kazi, P. Meinerzhagen, P.-E. Gaillardon, D. Sacchetto, Y. Leblebici, A. Burg, and G. De Micheli, “Energy/reliability trade-offs in low-voltage ReRAM-based non-volatile flip-flop design,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 11, pp. 3155–3164, 2014.
[30] Na, K. Ryu, J. Kim, S.-O. Jung, J. P. Kim, and S. H. Kang, “High-performance low-power magnetic tunnel junction based non-volatile flip-flop,” in 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, pp. 1953–1956, 2014.
[31] Qazi, A. Amerasekera, and A. P. Chandrakasan, “A 3.4-pJ FeRAM-enabled D flip-flop in 0.13-μm CMOS for nonvolatile processing in digital systems,” IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 202–211, Jan. 2014
[32] Wang, S. George, A. Aziz, S. Datta, V. Narayanan, and S. K. Gupta, “Ferroelectric transistor based non-volatile flip-flop,” in Proc. ACM Int. Symp. Low Power Electron. Design, pp. 10–15, 2016.
[33] Na, K. Ryu, J. Kim, S.-O. Jung, J. P. Kim, and S. H. Kang, “High performance low-power magnetic tunnel junction based non-volatile flip-flop,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1953–1956, Jun. 2014.
[34] Kimura, Hiromitsu, Takaaki Fuchikami, Kyoji Maramoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto. "A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability." In 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 21-24. IEEE, 2014.
[35] Na, Taehui, Kyungho Ryu, Jisu Kim, Seong-Ook Jung, Jung Pill Kim, and Seung H. Kang. "High-performance low-power magnetic tunnel junction based non-volatile flip-flop." In 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1953-1956. IEEE, 2014.
[36] Predictive Technology Model (PTM). Accessed: Jan. 3, 2019. [Online]. Available: http://ptm.asu.edu/
[37] Aziz, S. Ghosh, S. Dutta, and S. K. Gupta, “Physics-based circuit compatible SPICE model for ferroelectric transistors,” IEEE Electron Device Lett., vol. 37, no. 6, pp. 805–808, Jun. 2016.
[38] Raha et al., "Designing energy-efficient intermittently powered systems using spin-hall-effect-based nonvolatile sram". IEEE Trans. On VLSI Sys. (TVLSI), 26(2), pp. 294–307, 2018.