ارزیابی عملکرد آنالوگ و پارامترهای اثر کانال کوتاه روی ترانزیستور اثر میدان بر پایه عایق توپولوژیک

نوع مقاله : علمی-پژوهشی

نویسندگان

1 گروه مهندسی نانوالکترونیک - پژوهشکده علوم و فناوری نانو - دانشگاه کاشان

2 دانشکده مهندسی برق و کامپیوتر - دانشگاه کاشان

3 دانشگاه فنی و حرفه‌ای - کاشان

چکیده

در راستای ارزیابی مواد جدید برای طراحی و شبیه سازی ترانزیستورهای اثر میدان در ابعاد نانومتری، در این مقاله ویژگی‌های الکترونیکی ترانزیستور اثر میدان بر پایه عایق توپولوژیک شبیه‌سازی و بررسی می‌گردد. از آنجا که گپ انرژی در ناحیه کانال این ترانزیستور با استفاده از میدان مغناطیسی عمود قابل‌تنظیم می‌باشد، ابتدا با رسم نمودار جریان بر حسب ولتاژ گیت به‌ازای مقادیر مختلف میدان مغناطیسی عمود، مشخصه‌های جریان مستقیم (DC Characteristics) همچون نسبت جریان روشن به جریان خاموش و ولتاژ آستانه (Threshold voltage) و عوامل مؤثر بر این پارامترها تجزیه و تحلیل می‌گردد. سپس برای ارزیابی اثرات کانال کوتاه، دو پارامتر نوسان زیرآستانه (subthreshold slope) و میزان تنزل سد القاشده ناشی از ولتاژ درین (DIBL) مورد بررسی قرار می‌گیرد. نتایج به‌دست‌آمده برای (subthreshold slope) و (DIBL) به‌ازای مغناطش  به‌ترتیب مقادیرmV/dec 8.24 و 0.064 را نشان می‌دهد که برای کاربردهای ترانزیستوری بسیار مناسب می‌باشد. در نهایت مشخصه‌های آنالوگ (Analog Characteristics) ترانزیستور شبیه‌سازی‌شده، همچون ترارسانایی (Transconductance)، هدایت خروجی (Output conductance)، مقاومت خروجی (Output resistance) و بهره ولتاژ (Gain) به‌دست‌آمده و عوامل مؤثر بر این پارامترها مورد ارزیابی قرار می‌گیرد.

کلیدواژه‌ها


عنوان مقاله [English]

Evaluation of Analog Performance and Short Channel Effect Parameters on Field Effect Transistor based on Topological Insulations

نویسندگان [English]

  • M. Vali 1
  • D. Dideban 2
  • N. Moezi 3
1 Institute of Nanoscience and Nanotechnology, University of Kashan, Kashan, Iran
2 Depertment of Electrical and Computer Engineering, University of Kashan, Kashan, Iran
3 Technical and Vocational University, Kashan, Iran
چکیده [English]

In this paper, in order to evaluate new materials for design and simulation of the field effect transistors in nano dimensions, we simulate and investigate the electronic properties of a field effect transistor based of topological insulator. Since the energy gap in the channel region of this transistor is adjustable by a perpendicular magnetic field, first by obtaining the transfer characteristics, we analyze the DC characteristics such as Ion/Ioff ratio and the threshold voltage. Moreover, we evaluate the short channel effects (SCEs) including subthreshold slope (SS) and drain induced barrier lowering (DIBL).The obtained results for (SS) and (DIBL) for m=1 show the values of 8.24mV/dec and 0.064, respectively, which are very suitable for transistor applications. Finally we achieve the analog characteristics of the simulated field effect transistor such as transconductance, output conductance, output resistance and voltage gain and study the parameters affecting these figures of merits.

کلیدواژه‌ها [English]

  • Field effect transistor
  • topological insulator
  • Ion/Ioff ratio
  • threshold voltage
  • short channel effects
  • subthreshold slope
  • analog characteristics
  • transconductance
  • output conductance
  • output resistance
  • voltage gain
[1] K. Boucart and A. M. Ionescu, "Double-Gate Tunnel FET With High-kappa Gate Dielectric," IEEE Transactions on Electron Devices, vol. 54, no. 7, pp. 1733-1725, 2007.
[2] S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, "Performance comparison between pin tunneling transistors and conventional MOSFETs," IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 465-459, 2009.
[3] حامد نجفعلی‌زاده، علی‌اصغر اروجی "طراحی ساختاری از ترانزیستور ماسفت دو گیتی با به‌کار گیری دو ماده، اکسید هافلیم (HfO2) و سیلیسیم-ژرمانیوم (SiGe) در کانالی از جنس سیلیسیم (DM-DG)"دوره 47، شماره 1، بهار 1396، صفحه 304-299.
[4] علی‌اصغر اروجی، زینب رمضانی فر و عاطفه رحیمی فر     "ترانزیستور اثر میدان فلز-نیمه هادی در تکنولوژی سیلیسیم روی عایق با استفاده از یک تکه اکسید اضافی در کانال برای کاربردهای توان و فرکانس بالا" دوره 46، شماره 4، زمستان 1395، صفحه 6-1.
[5] Y. P. Chen, "Graphene and topological insulator based transistors: Beyond computing applications," in   70th Annual Device Research Conference (DRC),  pp. 37-38, 2012.
[6] M. Z. Hasan and C. L. Kane, "Colloquium: topological insulators," Reviews of Modern Physics, vol. 82, no. 4, pp. 3045-3067, 2010.
[7] F. Xiuet al., "Manipulating surface states in topological insulator nanoribbons," Nature nanotechnology, vol. 6, no. 4, pp216-221., 2011.
[8] Y. P. Chen, "Topological Insulator Based Energy Efficient Devices," in Proc. of SPIE, vol. 8373, pp. B1-B5, 2012.
[9] A. K. Geim and K. S. Novoselov, "The rise of graphene," Nature materials, vol. 6, no. 3, pp. 183-191, 2007.
[10] J. Linder, Y. Tanaka, T. Yokoyama, A. Sudb, and N. Nagaosa, "Interplay between superconductivity and ferromagnetism on a topological insulator," Physical Review B, vol. 81, no. 18, pp. 1-11, 2010.
[11] S. Datta, Quantum transport: atom to transistor. Cambridge University Press, 2005.
[12] R. Vali, "Spin filtering through Cd 1− yMgyTe/Cd 1− xMnxTe heterostructure," Physica E: Low-dimensional Systems and Nanostructures, vol. 69, no. 3, pp. 637-642, 2008.
[13] M.Vali, D. Dideban, N. Moezi, "A scheme for a topological insulator fi eld effect transistor " Physica E: Low-dimensional Systems and Nanostructures, vol. 40, pp. 360-363, 2015.
[14] Y. Zhang and F. Zhai, "Tunneling magnetoresistance on the surface of a topological insulator with periodic magnetic modulations," Applied Physics Letters, vol. 96, no. 17, pp. 172109-172111, 2010.
[15] J. Zhang and J. Yuan, "Electron transport with tunable ferromagnetic barriers on the surface of topological insulators," The European Physical Journal B, vol. 85, no.100, pp. 1-6, 2012.
[16] S. Datta, Electronic transport in mesoscopic systems. Cambridge university press, 1997.
[17] S. Ghazanfari, "Transfer Matrix Approach to One-Dimensional Electron Transport in Graphene Sheets with Piecewise Constant Potentials," Acta Physica Polonica A, vol. 123, no. 1, pp. 148-151, 2013.
[18] M. Katsnelson, K. Novoselov and A. Geim, "Chiral tunnelling and the Klein paradox in graphene," Nature physics, vol. 2, no. 9, pp. 620-625, 2006.
[19] L. Wang, K. Shen, S. Cho, and M. Wu, "A scheme for spin transistor with extremely large on/off current ratio," Journal of Applied Physics, vol. 104, no. 12, p. 123709, 2008.
[20] F. Zhai and P. Mu, "Tunneling transport of electrons on the surface of a topological insulator attached with a spiral multiferroic oxide," Applied Physics Letters, vol. 98, no. 022107, pp. 1-3, 2011.
[21] M. Akram and B. Ghosh, "Analog performance of double gate junctionless tunnel field effect transistor," Journal of Semiconductors, vol. 35, no. 7, pp. 074001(1)-074001(5), 2014.
[22] J.-P. Colingeet al., "Nanowire transistors without junctions," Nature nanotechnology, vol. 5, no. 3, pp. 225-229, 2010.
[23] S. K. Gupta and S. Baishya, "Analog and RF performance evaluation of dual metal double gate high-k stack (DMDG-HKS) MOSFETs," Journal of Nano-and Electronic Physics, vol. 5, no. 3, pp. 03008(1)-03008(8), 2013.
[24] R. Narang, M. Saxena, R. Gupta and M. Gupta, "Effect of temperature and gate stack on the linearity and analog performance of double gate tunnel FET," in Trends in Network and Communications: Springer, pp. 466-475, 2011.
[25] R. K. Baruah and R. P. Paily, "Analog performance of bulk planarjunctionless transistor (BPJLT)," in Third International Conference on Computing Communication & Networking Technologies (ICCCNT), , pp. 1-4, 2012.
[26] K. Boucart and A. M. Ionescu, "Length scaling of the double gate tunnel FET with a high-k gate dielectric," Solid-State Electronics, vol. 51, no. 11, pp. 1500-1507, 2007.
[27] D. Flandre, J.-P. Raskin and D. Vanhoenacker-Janvier, "SOI CMOS transistors for RF and microwave applications," International journal of high speed electronics and systems, vol. 11, no. 04, pp. 1159-1248, 2001.
[28] J. Chang, L. F. Register and S. K. Banerjee, "Topological insulator Bi2Se3 thin films as an alternative channel material in metal-oxide-semiconductor field-effect transistors," Journal of Applied Physics, vol. 112, no. 12, p. 124511, 2012.
[29] A. H. Bayani, D. Dideban, M. Vali and N. Moezi, "Germanene nanoribbon tunneling field effect transistor (GeNR-TFET) with a 10 nm channel length: analog performance, doping and temperature effects," Semiconductor Science and Technology, vol. 31, no. 4, pp. 1-7, 2016.
[30] M. S. Mobarakeh, N. Moezi, M. Vali and D. Dideban, "A novel graphene tunnelling field effect transistor (GTFET) using bandgap engineering," Superlattices and Microstructures, vol. 100, pp. 1221-1229, 2016.
[31] P. Razavi and A. A. Orouji, "Dual material gate oxide stack symmetric double gate MOSFET: improving short channel effects of nanoscale double gate MOSFET," in 11th International Biennial Baltic Electronics Conference, pp. 83-86, 2008.