مقاوم‌سازی الگوریتم‌های رمزنگاری در داخل FPGA به کمک PLL

نویسندگان

دانشکده مهندسی برق و کامپیوتر - دانشگاه زنجان

چکیده

امروزه اشتراک اطلاعات در سیستم‌های مخابراتی و کامپیوترها نیازمند امنیت بسیار بالایی است. در این میان، حملات کانال جانبی همواره به‌عنوان یکی از چالش‌های امنیتی در رمزنگاری سیستم‌ها می‌باشد، که برای حمله به ادوات رمزنگاری ازجمله کارت‌های هوشمند بکار می‌رود. در این مقاله هدف ارائه طرح جدیدی برای مقاوم‌سازی الگوریتم‌های رمزنگاری است که به‌صورت سخت‌افزاری در FPGA  پیاده شده‌است. اساس این طرح استفاده از حلقه فاز قفل شده PLL در الگوریتم‌های رمزنگاری AES می‌باشد که با به هم‌زدن میزان توان مصرفی و زمان‌های اجرای بخش‌های مختلف الگوریتم، مقاومت الگوریتم‌های رمزنگاری را در برابر حملات توان بالا می‌برد. این روش از دو تکنیک masking و hiding برای حفاظت کلید خصوصی رمزنگاری استفاده می‌کند، طرح پیشنهادی در تکنولوژی TSMC 65nm شبیه‌سازی شده و موفقیت قابل‌توجه نشان داده است، به‌طوری‌که توانسته است در رمزنگاری AES با هزینه سربار  13% در فضای اشغالی CMOS و افزایش 15 درصدی توان مصرفی، تنها فرکانس کاری را به اندازه 2% کم کرده و امکان به دست آوردن کلید صحیح برای حمله‌کننده را بسیار سخت نماید. همچنین، روش پیشنهادی بر روی FPGA پیاده‌سازی شده‌است و نتایج رضایت‌بخشی بر روی تعداد قابل قبولی از نمودار توان به‌دست آمده‌است.

کلیدواژه‌ها

عنوان مقاله [English]

Countermeasure cryptography algorithm by PLL to FPGA

نویسندگان [English]

  • V. Rashtchi
  • H. Mousavi
Faculty of Electrical and Computer Engineering, University of Zanjan, Zanjan, Iran
چکیده [English]

Now days, sharing data in communication systems and computers require high levels of Information security. Side channel attack is one of the methods which it is applied to attack cryptographic systems such as smart cards. In this paper, a new approach for countermeasuring cryptographic algorithms has been proposed and implemented on FPGA. The scheme is based on using Phase Locked Loop in AES algorithm which by disturbing power consumption pattern and execution time of different rounds, the resistance of the algorithm against power attack has been increased. Masking and hiding technique has been used to protect the encryption key. Overall, the proposed method has been simulated within TSMC 65nm technology platform and outstanding success has been obtained; in applying the technique to AES, the overhead was 13% in CMOS area, 15% in power consumption, 2% decrease in working frequency while finding the key became difficult for attackers. In addition, the proposed method has been implemented on FPGA and satisfactory results have been obtained for an acceptable number of samples of the power trace.

کلیدواژه‌ها [English]

  • Advanced Encryption Standard (AES)
  • Differential Power Analysis (DPA)
  • Power Analysis (PA)
  • power measurement
  • Field Programmable Gate Array (FPGA)

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