اشمیت تریگر CMOS شبه-تفاضلی خیلی کم ولتاژ 4/0ولت مبتنی‌بر اینورتر دیجیتال

نوع مقاله : علمی-پژوهشی

نویسندگان

دانشکده مهندسی برق و کامپیوتر- دانشگاه تربیت دبیر شهید رجایی

چکیده

در این مقاله، یک اشمیت تریگر شبه-تفاضلی مبتنی‌بر دیجیتال با ولتاژ تغذیه خیلی کم ارائه شده‌است. اشمیت تریگر پیشنهادی با الهام‌گیری از روند طراحی یک اشمیت تریگر آنالوگ طراحی شده‌است. مدار پیشنهادی تنها با استفاده از اینورترهای CMOS دیجیتال پیاده‌سازی شده‌است که از یک مقایسه‌گر تفاضلی متشکل از دو اینورتر CMOS و یک جفت اینورتر متقابل به‌عنوان فیدبک مثبت تشکیل شده‌است. مدار پیشنهادی تنها مدار اشمیت تریگر مبتنی‌بر دیجیتال است که در حالت تمام تفاضلی عمل می‌کند که دارای دو خروجی معکوس‌کننده و غیرمعکوس‌کننده به‌طور هم‌زمان است و در آن قابلیت تغییر مرکز هیسترزیس توسط ولتاژ ورودی فراهم شده‌است. اشمیت تریگر پیشنهادی در فرایند  CMOS0.18μm  با ولتاژ تغذیه 0.4 ولت شبیه‌سازی شده‌است. به‌دلیل تعداد ترانزیستورهای بسیار کم، مدار پیشنهادی مساحت تراشه‌ای به اندازهμm210×9.8 را اشغال می‌کند و تنها 6.64 نانووات توان مصرف می‌کند.

کلیدواژه‌ها

عنوان مقاله [English]

0.4-V Ultra-low-voltage Pseudo-differential CMOS Schmitt Trigger Based on Digital Inverter

نویسندگان [English]

  • Y. Bastan
  • F. Fazel
  • A. Nejati
  • P. Amiri
Faculty of Electrical and Computer Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran
چکیده [English]

In this paper, a digital pseudo-differential Schmitt trigger with very low supply voltage is proposed. The proposed Schmitt trigger is design by exploiting the design procedure of an analog Schmitt trigger. It is implemented only using digital CMOS inverters which is composed of a pseudo-differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair as positive feedback. The proposed circuit is the only digital Schmitt trigger which operates in fully-differential mode that has simultaneously two outputs of non-inverting and inverting and its hysteresis center can be changed by the input voltage. The proposed Schmitt trigger is simulated in 0.18 um CMOS process with 0.4 V supply voltage. Due to the very low number of transistors, the proposed circuit occupies 10×9.8 μm2 chip area and consumes only 6.64 nW power.

کلیدواژه‌ها [English]

  • Differential Schmitt trigger
  • digital inverter
  • cross-coupled inverter pair
  • ultra-low-voltage
  • CMOS

مراجع

[1] B. Razavi, Design of analog CMOS integrated circuits. NewYork, McGraw-Hill Education, 2017.
[2] Y. Bastan, M. Janipoor-Deylamani, and P. Amiri, “Fast-transient capacitor-less low-dropout regulator with input current-differencing and dynamic current-boosting,” Analog Integrated Circuits and Signal Processing, 2018.
[3]  مهدی حسین نژاد و حسین شمسی، «طراحی و شبیه‌سازی مبدل آنالوگ به دیجیتال لوله‌ای مبتنی‌بر مقایسه‌گر ولتاژ پایین»، مجله مهندسی برق دانشگاه تبریز، دوره 46، شماره 1، صفحه 98-87، بهار 1395.
[4]  خلیل منفردی و یوسف بلقیس‌آذر، «تقویت‌کننده کسکود تمام‌تفاضلی بازیابی تاشده بهبودیافته ولتاژ و توان پایین»، مجله مهندسی برق دانشگاه تبریز، دوره 48، شماره 1، صفحه 334-327، بهار 1397.
[5]    M. Asyaei, “A new low-power dynamic circuit for wide fan-in gates,” Integration, The VLSI Journal, vol. 60, pp. 263-271, Jan. 2018.
 [6] S. Weaver, B. Hershberg, and Un-KuMoon, “Digitally Synthesized Stochastic flash ADC using only standard digital cells,” IEEE Transaction on Circuits and Systems-I: Regular papers, vol. 61, no. 1, pp. 84-91, Jan. 2014.
 [7]    F. Fazel, Y. Bastan, and P.Amiri, “Design of fully digital 3-bit flash ADC based on logic gates,” IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI), pp. 516-521, Tehran, Iran, 2017.
 [8]    Sameer Thakre, Pankaj Srivastava, “Design and analysis of low-power high-speed clocked digital comparator,” Proceedings of 2015 Global Conference on Communication Technologies, 2015.
[9]    P. S. Crovetti, “A Digital-based virtual voltage reference,” IEEE Transaction on Circuits and Systems-I: Regular papers, vol. 62, no. 5, May 2015.
[10] J. Kulkarni, K. Kim, and K. Roy, “A 160 mV robust schmitt trigger based subthreshold SRAM,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 2303-2313, 2007.
[11] D. Park, J. Rhee, and Y. Joo, “Wide dynamic range and high SNR self-reset CMOS image sensor using a Schmitt trigger,” IEEE Sensors, pp. 294-296, Lecce, Italy, 2008.
[12] H. Kim, H. Kim, and W. Chung, “Pulsewidth Modulation Circuits Using CMOS OTAs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp. 1869-1878, 2007.
[13] CMOS Schmitt Trigger.A Uniquely Versatile Design Component, Fairchild Semiconductor Application Note 140, June, 1975.
[14]   W. M. Kader, H. Rashid, M. Mamun, and M. A. S. Bhuiyan, Advancement of CMOS Schmitt Trigger Circuits, Modern Applied Science, Published by Canadian Center of Science and Education, 2012.
[15]   F. Yuan, “Differential CMOS Schmitt trigger with tunable    hysteresis,” Analog Integrated Circuit and Signal Processing, vol. 62, no. 2, pp. 245-248, 2010. 
 [16] K. Lin, X. Wang, X. Zhang, and B. Wang, “A PVT-independent schmitt trigger with fully adjustable hysteresis threshold voltage for low power 1-bit digitization applicationds,” IEICE Electronics Express, vol. 13, no. 17, pp. 1-9, August, 2016.
 [17] A. W. Kadu, M. Kalbande, “Design of low power schmitt trigger logic gates using VTCMOS,” 2016 Online International Conference on Green Engineering and Technologies (IC-GET), 2016.
[18] F. Yuan, “A high-speed differential CMOS Schmitt trigger with regenerative current feedback and adjustable hysteresis,” Analog Integrated Circuits and Signal Processing, vol. 63, no. 1, pp. 121-127, 2010.
[19] A. Nejati, Y. Bastan, and P.  Amiri, “0.4 V ultra-low voltage differential CMOS Schmitt trigger,” Iranian Conference on Electrical Engineering (ICEE), pp. 532-536, IEEE, Tehran, Iran (2017).
[20] R. Jani, and S. Oza, “Low power differential CMOS schmitt trigger with adjustable hysteresis,” Theoretical and Applied Electrical Engineering, vol. 15, no. 5, Dec. 2017.
 
 [21] G. Hang, and G. Zuu, “A new schmitt trigger with n-channel neuron-MOS transistor,” 11th International Conference on Natural Computation (ICNC), Zhangjiajie, China, 2015.
[22] M. Janveja, A. Khan, and V. Niranjan, “Performance evaluation of subthreshold schmitt trigger using body bias techniques,” International Conference on Computational Techniques in Information and Communication Technologies (ICCTICT), New Delhi, India, 2016.
[23] S. Park, K. Kim, H. A. Huynh, S. Joo, and S. Y. Kim, “EM noise immunity enhancement using schmitt trigger logic gates in CMOS process,” URSI Asia-Pacific Radio Science Conference (URSI AP-RASC), pp. 915-918, Seoul, South Korea 2016.
[24] C. Pham, “CMOS schmitt trigger circuit with controllable hysteresis using logical threshold voltage control circuit,” 6th IEEE/ACIS International Conference on Computer and Information Science (ICIS), 2007.
 
[25] P. Amiri, A. Nabavi, and S. Mortazavi, “Low distortion CMOS class-D amplifier with double-band hysteresis,” IEICE Electronics Express, vol. 7, no. 4, pp. 273-280, 2010.
 
[26] M. Ramdani, E. Sicard, A. Boyer, S. B. Dhia, J. J. Whalen, T. H. Hubing, M. Coenen, and O. Wada, “The electromagnetic compatibility of integrated circuits-Past, present, and future,” IEEE Trans. Electromagn. Compat. vol. 51, no. 1, pp. 78–100, February, 2009.
 
[27] D. Bol, R. Ambroise, D. Flandre, and J. Legat, “Interests and limitations of technology scaling for subthreshold logic,” IEEE Trans. Very Large Scale Integr. Syst., vol. 17, no. 10, pp. 1508–1519, October, 2009.
 [28] A.Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-threshold Design for Ultra Low-Power Systems, Springer, 2006.
[29] A. Nejati, Y. Bastan, P. Amiri, and M. H. Maghami, “A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable Hysteresis,” Journal of Circuits, Systems and Computers, 2018.

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