طراحی ALU تحمل‌پذیر اشکال با روش جدید پیاده‌سازی کد برگر

نوع مقاله : علمی-پژوهشی

نویسندگان

1 دانشکده مهندسی برق و کامپیوتر - دانشگاه علم و صنعت

2 دانشکده فنی مهندسی - گروه برق - دانشگاه زنجان

چکیده

واحد محاسبه و منطق از حساس‌ترین واحدهای سازنده یک پردازنده است که اکثر دستورهای یک پردازنده توسط این بخش انجام می‌شود. افزونگی زمانی یکی از مناسب‌ترین روش‌های مقابله با خطای گذرا است. در اغلب روش‌های افزونگی زمانی لازم است ابتدا خطا آشکار شود، بنابراین وجود مدارهای آزمون در کنار روش‌های افزونگی زمانی ضروری است. از بزرگ‌ترین ایرادهای مدارهای آزمون سربار سخت‌افزاری بالای این مدارها است که باعث می‌شود طراحان در طراحی مدارهای کوچک مجبور به استفاده از روش‌های غیرمعمول شوند. در این مقاله روش جدیدی برای پیاده‌سازی مدار چک کننده برگر ارائه‌شده است در این روش از مدارات حالت جریان جهت پیاده‌سازی کد برگر استفاده‌شده است که ویژگی‌های آن سرعت بالاتر و سخت‌افزار موردنیاز کمتر است. با توجه به نتایج توان مصرفی مدار پیشنهادی نسبت به مدار دیجیتال به‌طور متوسط تا حدود 51 درصد کاهش‌یافته است و سطح اشغالی مدار آزمون حالت جریان 74.3 درصد کمتر از سطح مصرفی مدار معادل دیجیتال است. به‌طور متوسط هزینه مدار برگر حالت جریان (حاصل‌ضرب توان مصرفی در تأخیر و سطح مصرفی)، 91 درصد کمتر از پیاده‌سازی برگر دیجیتال معادل است.

کلیدواژه‌ها

عنوان مقاله [English]

Fault Tolerant ALU Designing based on New Implementation of Berger Code

نویسندگان [English]

  • A. Towhidy gol 1
  • R. Omidi 2
  • K. Mohammadi 1
1 School of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran
2 Faculty of Engineering, University of Zanjan, Zanjan, Iran
چکیده [English]

ALU is one of the most sensitive units of a processor, which most of the instructions of a processor are executed by this section. In most of the Architecture methods for mitigation of fault such as temporal redundancy, it is necessary to detect the errors first. Hardware overhead of test circuits is one of the most important disadvantages for testing small circuits which makes designers to use unusual methods in the design of small circuits. In this Article, a new implementation method for Berger code has been used to detect the error and compared with the previous method that is based on the Berger code. In the proposed method, the current mode circuits are employed to reduce the cost of the Berger code implementation. This circuit has higher speed and less hardware complexity than conventional implementations of Berger code. According to the result of this article, the Power of current mode Berger has been reduced at a rate of 51%, and the area of current mode Berger has been reduced at a rate of 74.3% and also the total cost of the Berger circuit (Power*Delay*Area) has been reduced at a rate of 91%.

کلیدواژه‌ها [English]

  • Fault Tolerant
  • Redundancy
  • Current Mode Circuit
  • Residue Code
  • Berger Code

مراجع

[1]           J. F. Ziegler et al., "IBM experiments in soft fails in computer electronics (1978–1994)," IBM journal of research and development, vol. 40, no. 1, pp. 3-18, 1996.
[2]           F. Wang and V. D. Agrawal, "Single event upset: An embedded tutorial," IEEE 21st International Conference on VLSI Design,)VLSID(. pp. 429-434, 2008.
[3]           W. Heidergott, "SEU tolerant device, circuit and processor design," in Design Automation Conference, 2005. Proceedings. 42nd, 2005, pp. 5-10: IEEE.
[4]           B. Narasimham et al., "Characterization of digital single event transient pulse-widths in 130-nm and 90-nm CMOS technologies," IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2506-2511, 2007.
[5]           M. Santarini, "Cosmic radiation comes to ASIC and SOC design-As 1C-process geometries shrink, single-event effects, such as soft errors and latch-ups, will soon become primary concerns for designers of ASICs and," Edn, vol. 50, no. 10, pp. 46-60, 2005.
[6]           N. Mahatme et al., "Impact of technology scaling on the combinational logic soft error rate," in Reliability Physics Symposium, 2014 IEEE International, 2014, pp. 5F. 2.1-5F. 2.6: IEEE.
[7]           A. Dixit and A. Wood, "The impact of new technology on soft error rates," in Reliability Physics Symposium (IRPS), 2011 IEEE International, 2011, pp. 5B. 4.1-5B. 4.7: IEEE.
[8]           R. K. Iyer and D. J. Rossetti, "A measurement-based model for workload dependence of CPU errors," IEEE Transactions on Computers, vol. 100, no. 6, pp. 511-519, 1986.
[9]           P. Duba and R. Lyer, "Transient fault behavior in a microprocessor-A case study," in IEEE International Conference onComputer Design 1988, pp. 272-276.
[10]         ثابت سروستانی, محمدامین؛ بهنام قوامی و محسن راجی «کاهش نرخ خطای نرم چندگانه مدارهای ترکیبی مبتنی بر اندازه گذاری دروازه‌ها بر مبنای پارامتر حساسیت»، فصلنامه مهندسی برق دانشگاه تبریز، دوره47، شماره(2)، صفحه 445-454، تابستان ۱۳۹۶.
 
[11]         R. H. Maurer, M. E. Fraeman, M. N. Martin, and D. R. Roth, "RHarsh Environments: Space Radiation," Johns Hopkins APL technical digest, vol. 28, no. 1, p. 17, 2008.
[12]         نبی پور, سعیده؛ جواد جاویدان و غلامرضا زارع فتین «طراحی یک دیکدر BCH بهینه جهت افزایش اطمینان در ذخیره سازی اطلاعات و تصحیح خطا در حافظه‌های فلش»، فصلنامه مهندسی برق دانشگاه تبریز، دوره 46، شماره (3)، صفحه 319-331 ، پاییز ۱۳۹۵.
[13]         X. Kavousianos, D. Nikolos, G. Foukarakis, and T. Gnardellis, "New efficient totally self-checking Berger code checkers," INTEGRATION, the VLSI journal, vol. 28, no. 1, pp. 101-118, 1999.
[14]         R. Omidi and H. Zarrabi, "New Protection Technique Against Unidirectional MEUs for FIR Filters," Circuits, Systems, and Signal Processing, pp. 1-16, 2017.
[15]         E. Ossi, D. Limbrick, W. Robinson, and B. Bhuva, "Soft-error mitigation at the architecture-level using berger codes and instruction repetition," in Proceedings of the IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE’09), 2009.
[16]         V. Sapozhnikov, V. Sapozhnikov, D. Efanov, and A. Blyudov, "Analysis of error-detection possibilities of CED circuits based on Hamming and Berger codes," in 2013 11th East-West Design and Test Symposium (EWDTS), 2013, pp. 1-8: IEEE.
[17]         V. Sapozhnikov, V. Sapozhnikov, and D. Efanov, "Search algorithm for fully tested elements in combinational circuits, controlled on the basis of berger codes," in 2017 IEEE East-West Design & Test Symposium (EWDTS), 2017, pp. 1-10: IEEE.
[18]         F. Huemer and A. Steininger, "Advanced Delay-Insensitive 4-Phase Protocols," in 2018 Austrochip Workshop on Microelectronics (Austrochip), 2018, pp. 50-55: IEEE.
[19]         G. P. Acharya and M. A. Rani, "Berger code based concurrent online self-testing of embedded processors," Journal of Semiconductors, vol. 39, no. 11, p. 115001, 2018.
[20]         W. W. Peterson, "On checking an adder," IBM Journal of Research and Development, vol. 2, no. 2, pp. 166-168, 1958.
[21]         S. J. Piestrak, "Self-testing checkers for arithmetic codes with any check base A," in IEEE International Symposium on Fault Tolerant Systems . , 1991, pp. 162-167.
[22]         I. Sayers and D. Kinniment, "Low-cost residue codes and their application to self-checking VLSI systems," IEEE Proceedings  (Computers and Digital Techniques), vol. 132, no. 4, pp. 197-202, 1985.
[23]         S.-H. Shieh and W.-S. Tong, "Berger Code Totally Self-Checking Checker Design for Embedded Adder Cores," Proceedings of the 5th Symposium on Smart Life Science and Technology (Part 1), 2010.
[24]         N. Homma, T. Aoki, and T. Higuchi, "Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic," in IEEE 36th International Symposium on Multiple-Valued Logic, 2006. (ISMVL 2006). , 2006, pp. 2-2.
[25]         A. Saed, M. Ahmadi, and G. A. Jullien, "Arithmetic circuits for analog digits," in IEEE 29th International Symposium on Multiple-Valued Logic, , 1999, pp. 186-191.
[26]         T. Temel and A. Morgul, "Implementation of multi-valued logic gates using full current-mode CMOS circuits," Analog Integrated Circuits and Signal Processing, vol. 39, no. 2, pp. 191-204, 2004.
[27]         F. Yuan, "Voltage-Mode Versus Current-Mode: A Critical Comparison," CMOS Current-Mode Circuits for Data Communications, pp. 1-12, 2007.
[28]         J. Engblom, "Why SpecInt95 should not be used to benchmark embedded systems tools," ACM SIGPLAN Notices, vol. 34, no. 7, pp. 96-103, 1999.

فایل ها

هم رسانی

ارجاع به این مقاله

آمار