طراحی یک مدار ضرب‌کننده آنالوگ برمبنای حلقه translinear در حالت جریان با توان مصرفی پایین و دقت بالا

نوع مقاله : علمی-پژوهشی

نویسندگان

1 باشگاه پژوهشگران جوان و نخبگان - واحد ارومیه - دانشگاه آزاد اسلامی

2 گروه مهندسی برق- واحد ارومیه- دانشگاه آزاد اسلامی

چکیده

در این مقاله یک مدار ضرب‌کننده CMOS آنالوگ چهار ربع جدید در حالت جریان که مبتنی بر دو جفت حلقه translinear دوگان می‌باشد ارائه می‌گردد. ویژگی‌های مهم مدار عبارتند از پهنای باند بالا، توان مصرفی کم و آزادبودن از اثر بدنه،که علت اصلی آن دوگان بودن مدار به این صورت که در هر حلقه translinear دوگان از دو NMOS و دو PMOS استفاده شده است. علاوه‌بر این، اعوجاج هارمونیک ناشی از ناهمگونی در سیگنال‌های ورودی (IX , IY)، پارامترهای هدایت انتقالی(K)  و ولتاژ آستانه (Vth) مورد بحث قرار گرفته است که نتایج حاکی از این است که مدار در برابر ناهمگونی بسیار مقاوم می‌باشد. به‌منظور بررسی عملکرد درست مدار ضرب‌کننده، از آن در دو کاربرد پراستفاده یعنی مدولاتور دامنه و دو برابرکننده فرکانس استفاده شده است که نتایج شبیه‌سازی آن ارائه شده است. این مدار با استفاده از شبیه ساز HSPICE با مدل TSMC مرحله 49 (BSIM3v3) در تکنولوژی 0.18 میکرومتر استاندارد CMOS طراحی و شبیه سازی شده است. که نتایج حاکی از خطای غیرخطی 0.62 درصد، اعوجاج هارمونیک کل 1/1 در فرکانس 1 مگا هرتز، پهنای باند 1.15 گیگا هرتز و حداکثر توان مصرفی 93.7 میکرو وات می‌باشد.

کلیدواژه‌ها


عنوان مقاله [English]

A New Highly Accurate Translinear Based CMOS Multiplier in Current Mode with Low Power Dissipation

نویسندگان [English]

  • T. Aghaei 1
  • A. Naderi 2
1 Young researchers and elite club, Urmia Branch, Islamic Azad University, Urmia, Iran
2 Department of Electrical-Electronics Engineering Urmia Branch, Islamic Azad University, Urmia, Iran
چکیده [English]

This paper deals with a new strategy for design of analog multiplier which operates in four quadrant. The proposed circuit employs the dual translinear principle with composition of NMOS and PMOS transistors, simultaneously. The important achievements of the circuit are its wide bandwidth, low power consumption as well as the body effect free performance. In order to demonstrate efficiency of the circuit, harmonic distortion analysis due to the mismatch in input signals (IX , IY), transconductance parameters (K) and threshold voltage (Vth) are discussed in detail, and the obtained relations verify the simulation results and indicate the robustness of the circuit in the presence of mismatch. Also, to validate the circuit performance, it is used in two useful applications of amplitude modulator and frequency doubler, and the simulation results of them are presented. Additionally, the Monte Carlo analysis for transistor parameters as well as the temperature variation results demonstrate stable performance of the circuit. This circuit is designed and simulated using HSPICE software with TSMC and level 49 parameters (BSIM3v3) in 180nm technology. The simulation results demonstrate a linearity error of 0.69%, a THD of 1.05% in 1MHz, a -3dB bandwidth of 1.17GHz and a maximum power consumption of 93µW.  

کلیدواژه‌ها [English]

  • Analog multipliers
  • translinear loop
  • body effect
  • four-quadrant
  • power consumption
  • bandwidth
[1]      Y. Ishiguchi, D. Isogai, T. Osawa and S. Nakatake, “Analog perceptron circuit with DAC-based multiplier,” Integration, the VLSI journal, vol. 63, pp. 240-247, 2018.
[2]      W. Liu and S. I. Liu, “Design of a CMOS low-power and low-voltage four-quadrant analog multiplier,” Analog Integr CircS, vol. 63, no. 2, pp. 307-312, 2010.
[3]      H. Sajjadi-Kia, “An analog cell and its applications in analog signal processing,” Int. J. Circ Theory App, vol. 63, pp. 195-201, 2011.
[4]      V. J. S. Oliveira and N. Oki, “Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS technology,” Analog Integrated Circuits and Signal Processing, vol. 65, no. 1, pp. 61-66, 2010.
[5]      M. M. Maryan and S. J. Azhari, “A MOS translinear cell-based configurable block for current-mode analog signal processing,” Analog Integr. Circuits Signal Process, vol. 92, no. 1, pp. 1-13, 2017.
[6]      حسین مرادی فراهانی و جواد عسگری، «طراحی کنترل‌کننده عصبی- فازی نوع-2»، مجله مهندسی برق، جلد 43، شماره 1، صفحات 63-73، دانشگاه تبریز، 1392.
[7]      فرشاد گودرزی و سیروس طوفان، «بهبود مدار آشکارساز فاز- فرکانس مبتنی بر لچ پالس برای افزایش ناحیه تشخیص و فرکانس کاری مدار»، مجله مهندسی برق، جلد 48، شماره 1، صفحات 283-289، دانشگاه تبریز، 1397.
[8]      S. C. Lui, J. Kramer, G. Indiveri, T. Delbruck and R. Douglas, “Analog VLSI: Circuits and Principles,” Cambridge, MA, USA: Massachusetts Institute of Technology Press, 2002.
[9]      I. M. Filanovsky and H. Baltes, “CMOS two-quadrant multiplier using transistor triode regime,” IEEE J Solid-St Circ, vol. 27, no. 5, pp. 831-833, 1992.
[10]      E. S. Al-Suhaibani and A. M. Al-Absi, “A compact CMOS current mode analog multi-functions circuit,” Analog Integr Circ Sig Process, vol. 84, no. 3, pp. 471-477, 2015.
[11]      K. Tanno, O. Ishizuka and Z. Tang, “Four-quadrant CMOS current-mode multiplier independent of device parameters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 5, pp. 473-477, 2000.
[12]      I. Makwana and V. Shet, “A low power high bandwidth four quadrant analog multiplier in 32 nm CNFET technology,” International Journal of VLSI design & Communication Systems (VLSICS), vol. 3, no. 2, pp. 73-83, 2012.
[13]      S. Keles and H. H. Kuntman, “Four quadrant FGMOS analog multiplier,” Turk J Elec Eng & Comp Sci, vol. 19, no. 2, pp. 291-301, 2011.
[14]      S. Soltany and A. Rezai, “A new low power four quadrant analog multiplier,” Information Technology and Computer Science, vol. 106, pp. 33-36, 2015.
[15]      S. Soltany and A. Rezai, “A novel low power and low voltage bulk-input four-quadrant analog multiplier in voltage mode,” International Journal of Multimedia and Ubiquitous Engineering, vol. 11, no. 1, pp. 159-168, 2016.
[16]      C. Popa, “Improved accuracy current-mode multiplier circuits with applications in analog signal processing,” IEEE Trans.Very Large Scale Integr. VLSI Syst, vol. 22, no. 2, pp. 443–447, 2014.
[17]      M. Hashiesh, S. Mahmoud and A. M. Soliman, “New four-quadrant CMOS current-mode and voltage-mode multipliers,” Analog Integr. Circuits Signal Process, vol. 45, no. 3, pp. 295–307, 2005.
[18]      A. Demosthenous and M. Panovic, “Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI,” IEEE Trans. Circuits Syst. I, vol. 52, no. 9, pp. 1721–1731, 2005.
[19]      A. U. Keskin, “A four quadrant analog multiplier employing CDBA,” Analog Integr. Circuits Signal Process., vol. 40, no. 1, pp. 99–101, 2004.
[20]      E. Yuce, “Voltage-mode multiplier implementation employing current conveyors,” Electron. World, vol. 112, no. 1850, pp. 45–47, 2006.
[21]      A. Zeki, A. U. Keskin and A. Toker, “DXCCII-based four-quadrant analog multipliers using triode MOSFETs,” in Proc. 4th ELECO, Bursa, pp. 41–45, 2005.
[22]      E. Yuce, “Design of a simple current-mode multiplier topology using a single CCCII+,” IEEE Transactions on Instrumentation and Measurement, vol. 57, no. 3, pp. 631–637, 2008.
[23]      M. T. Abuelma’atti and M. A. Al-Qahtani, “A current-mode current controlled current-conveyor-based analogue multiplier /divider,” Int. J.Electron., vol. 85, no. 1, pp. 71–77, 1998.
[24]      M. T. Abuelma’atti, “A novel analogue current-mode current-controlled frequency divider/multiplier,” Int. J. Electron., vol. 89, no. 6, pp. 455– 465, 2002.
[25]      K. Anuntahirunrat, W. Tangsrirat, V. Riewruja and W. Surakampontorn, “Sinusoidal frequency doubler and full-wave rectifier based on translinear current-controlled current conveyors,” Int. J. Electron., vol. 91, no. 4, pp. 227–239, 2004.
[26]      A. Naderi and S. Ozoguz, “Design Of High-Linear, High-Precision Analog Multiplier Free From Body Effect,” Turkish Journal of Electrical Engineering and Computer Sciences, vol.24, no. 3, pp. 820-832, 2016.
[27]      I. Aloui, N. Hassen and K. Besbes, “A CMOS current mode four quadrant analog multiplier free from mobility reduction,” AEU - International Journal of Electronics and Communications, vol. 82, pp. 119-126, 2017.
[28]      M. Kumngern and U. Torteanchai, “A CMOS current-mode multiplier/divider using a current amplifier, ” Proceedings of the 7th International Power Engineering and Optimization Conference (PEOCO), pp. 742–745, 2013.
[29]      M. Gravati, M. Valle, G. Ferri, N. Guerrini and L. Reyes, “A novel current-mode very low power analog CMOS four quadrant multiplier,” IEEE 2005 Solid State Circuits Conference, pp. 495-498, 2005.
[30]      M. Kumngern and D. Kobchai. “Versatile dual-mode class-AB four-quadrant analog multiplier,” Int J Signal Process, vol. 2, no. 8, pp. 214-221, 2005.
[31]      A. Alikhani and A. Ahmadi. “A novel current-mode four-quadrant CMOS analog multiplier/divider,”. Int J Electron Comm, vol. 66, no. 7, pp. 581-586, 2012.
[32]      A. Lopez-Martin, A. Carlosena. “Current-mode multiplier/divider circuits based on the MOS translinear principle,” Analog Integr Circ S, vol. 28, no. 3, pp. 265-278, 2001.
[33]      S. Menekay, R. Tarcan and H. Kuntman, “Novel high-precision current-mode circuits based on the MOS-translinear principle,” Int J Electron Comm, vol. 63, no. 11, pp. 992-997, 2009.
[34]      S. Kaedi and E. Farshidi. “A new low voltage four-quadrant current mode multiplier,”  IEEE 2012 20th Iranian Conference on Electrical Engineering, pp. 160-164, 2012.
[35]      M. A. Al-Absi and I. A. As-Sabban, “A new highly accurate CMOS current-mode four-quadrant multiplier,” Arab J Sci Eng, vol. 40, pp. 551-558, 2015.
[36]      A. Fabre, “New formulation to describe translinear mixed cells accurately,” Proc Inst Elect Eng,vol. 141, no. 3, pp. 167–73, 1994.
[37]      H. A. Jafari, and Z. Abbasi and S. J. Azhari, “An offset-free high linear low power high speed four-quadrant MTL multiplier,” Italian Journal of Science & Engineering, vol. 1, no. 3, pp. 129–134, 2017.
[38]      A. Alikhani and A. Ahmadi, “A novel current-mode four-quadrant CMOS analog multiplier/divider,” Int J Electron Comm, vol. 66, no. 7, pp. 581–586, 2012.
[39]      S. Menekay, R. Tarcan and H. Kuntman, “Novel high-precision current-mode circuits based on the MOS-translinear principle,” Int J Electron Comm 2009, vol. 63, no. 11, pp. 992–997, 2009.
[40]      S. Kaedi and E. Farshidi, “A new low voltage four-quadrant current mode multiplier,” In: IEEE 2012 20th Iranian Conference on Electrical Engineering; Tehran, Iran. New York, NY, USA: IEEE, pp. 160-164, 2012.
[41]      I. Chaisayun, S. Piangprantong, K. Dejhan, (2012), “Versatile analog squarer and multiplier free from body effect. Analog Integrated Circuits and Signal Processing,” vol. 71, no. 3, pp. 539-547, 2012.
[42]      E. Ibaragi, A. Hyogo and K. Sekine, “A CMOS analog multiplier free from mobility reduction and body effect,” Analog Integrated Circuits and Signal Processing, vol. 25, no. 3, pp. 281-290, 2000.
[43]      A. Naderi, A. Khoei, K. Hadidi and H. Ghasemzadeh, “A new high speed and low power four-quadrant CMOS analog multiplier in current mode, ” AEU-Int. J. Electron. Commun, vol. 63, no. 9, pp. 769–775, 2009.
[44]      C. Abel, S. Sakurai, E. Larsen and M. Ismail, “Four-quadrant CMOS/BiCMOS multipliers using linear-region MOS transistors,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 273–276, 1994.
[45]      Y. Igarashi, A. Hyogo and K. Sekine, “Design of very low-distortion, four-quadrant analog multiplier-type CMOS-OTA considering variation of mobility according to the gate voltage,” Electron. Commun. Jpn. (Part II: Electron.), vol. 77, no. 7, pp. 65–76, 1994.
[46]      A. Naderi, H. Mojarrad, H. Ghasemzadeh, A. Khoei, and K. Hadidi, “Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed, ” EUROCON’2009. IEEE, pp. 282-287, 2009.
[47]      J. K. Seon, “Design and application of precise analog computational circuits, ” Analog Integr. Circuits Signal Process, vol. 54, no. 1, pp. 55–66, 2008.
[48]      S. Keles and H. H. Kuntman, “Four quadrant FGMOS analog multiplier,” Turk J Elec Eng & Comp Sci, vol. 19, no. 2, pp. 291-301, 2011.
[49]      V. J. Oliveira and N. Oki, “Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process, Analog Integr. Circuits Signal Process, vol. 65, no. 1, pp. 61–66, 2010.
[50]      A.S. Nandini., S. Madhavan and Dr chirag Sharma, “Design and Implementation of Analog Multiplier with Improved linearity” nternational Journal of VLSI design & communication systems (VLSICS), vol. 3, no. 5, pp. 631-637, 2012.
[51]      H.–J. Song and C.-K. Kim, “An MOS four-quadrant analog multiplier using simple two-input squaring circuit with source follower,” IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 841-848, 1990.
[52]      S-I. Liu and C-C. Chang, “CMOS analog divider and four-quadrant multiplier using pool circuits,” IEEE Journal Solid-State Circuits, vol. 30, no.9, pp. 1025-1029, 1995.
[53]      N. Beyraghi, A. Khoei, and K. Hadidi, “CMOS design of a four quadrant multiplier based on a novel squarer circuit,” Analog Integr. Circuits Signal Process, vol. 80, no. 3, pp. 473–481, 2014.
[54]      I. Navarro, A. J. Lopez-Martin, C A. De La Cruz-Bias, A. Carlosena, “A compact four-quadrant floating-gate MOS multiplier,” AnalogIntegrated Circuits and Signal Processing, vol. 41, no. 2-3, pp. 159-166, 2004.
J. M. A. Miguel, C A. De La Cruz Blas and A. Lopez-Martin, “Fully differential current-mode CMOS triode translinear multiplier,” IEEE T Circuits Syst, vol. 58, no. 1, pp. 21-25, 2011.
[55]      F. Khateb, “Bulk-driven floating-gate and bulk-driven quasi-floating-gatetechniques for low-voltage low-power analog circuits design,” International Journal of Electronics and Communications (AEÜ), vol. 68, no. 1, pp. 64-72, 2014.
[56]      A. K. M. Mahfuzul Islam, “Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 7, no. 1, pp. 81-91, 2017.
[57]      A. Panigrahi and P. K. Paul, “A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion,” Analog Integrated Circuits and Signal Processing, voL 75, no. 2, pp. 237-243, 2013
[58]      C. A. De La Cruz-Blas, G. Thomas-Erviti, J. M. Algueta-Miguel and A. López-Martín, “CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques,” INTEGRATION, the VLSI journal, vol. 59, pp. 243-246, 2017.
[59]      X. Xin, J. Cai, R. Xie and P. Wang, “Voltage-mode ultra-low power four quadrant multiplier using subthreshold PMOS,” IEICE Electronics Express, vol. 14, no. 6, pp. 1-8, 2017.
[60]      M. A. Al-Absi, A. Hussein and M. TaherAbuelma’atti, “A Low Voltage and Low Power Current-Mode Analog Computational Circuit,” Circuits Syst Signal Process, vol. 32, no. 1, pp. 321-331, 2013.
[61]      R. Wu and J. Xing, “MOS translinear principle based analog four-quadrant multiplier,” IEEE 2012 International Conference on Anti-Counterfeiting, Security and Identication, pp. 1-4, 2012.