مدار دینامیکی جدید برای طراحی مقایسه‌کننده نشانه توان پایین

نویسنده

دانشکده فنی و مهندسی - دانشگاه دامغان

چکیده

در این مقاله یک مدار دینامیکی جدید برای کاهش توان مصرفی مقایسه‌کننده‌های نشانه پیشنهاد می‌شود. برای کاهش توان مصرفی در مدار دینامیکی پیشنهادی از ترانزیستورهای NMOS برای پیش‌بار گره دینامیکی استفاده شده است. بدین طریق دامنه تغییرات ولتاژ گره دینامیکی کم شده و توان مصرفی کاهش می‌یابد. شبیه‌سازی گیت‌های OR عریض و مقایسه‌کننده‌های نشانه 40 بیتی با استفاده از نرم‌افزار HSPICE در فناوری 90 نانومتر CMOS انجام شده است. نتایج شبیه‌سازی گیت‌های OR 32 بیتی در تأخیر یکسان، 42% کاهش توان و 1.68 برابر بهبود مصونیت در برابر نویز را نسبت به مدار دینامیکی متداول نشان می‌دهند. همچنین نتایج شبیه‌سازی بیانگر 52% و 16% کاهش به‌ترتیب در توان مصرفی و تأخیر مقایسه‌کننده نشانه پیشنهادی نسبت به نوع متداول آن تحت مصونیت در برابر نویز یکسان است.

کلیدواژه‌ها

عنوان مقاله [English]

New Dynamic Circuit for Low Power Tag Comparator Design

نویسنده [English]

  • M. Asyaei
School of Engineering, Damghan University, Damghan, Iran
چکیده [English]

In this paper, a new dynamic circuit is proposed to reduce power consumption of tag comparators. To reduce the power consumption in the proposed dynamic circuit, NMOS transistors are used to precharge the dynamic node. In this way, voltage swing on the dynamic node is decreased and hence the power consumption is reduced. Simulation of wide fan-in OR gates and 40-bit tag comparators are done using HSPICE simulator in a 90nm CMOS technology model. Simulation results exhibit 42% power reduction and 1.68× noise-immunity improvement at the same delay compared to the conventional dynamic circuit for 32-bit OR gates. Moreover, simulation results demonstrate 52% and 16% reduction in the power consumption and delay of the proposed tag comparator, respectively, at the same noise immunity compared to the conventional one

کلیدواژه‌ها [English]

  • Tag comparator
  • dynamic circuits
  • leakage current
  • noise immunity

مراجع

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