[1] پرویز امیری، محمود صیفوری، بابک آفرین و آوا هدایتیپور، «طراحی پیشتقویتکننده RGC کم نویز مدار مجتمع CMOS با پهنای باند GHz20 و بهره dBΩ60»، مجله مهندسی برق دانشگاه تبریز، دوره 46، شماره 2، صفحه 23-15، تابستان 95.
[2] اکرم امیری و سیروس طوفان، «مبدل زمان به دیجیتال رزولوشن بالا و توان مصرفی کم مبتنی بر اسیلاتور حلقوی چند مسیره»، مجله مهندسی برق دانشگاه تبریز، دوره 46، شماره 3، صفحه 50- 45، پاییز 95.
[3] A. Tsormpatzoglou, C.A. Dimitriadis, R. Clerc, Q. Rafhay, G. Pananakakis and G. Ghibaudo, “Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1943-1952, 2007.
[4] I. Ferain, C.A. Colinge and J. Coling, “Multigate transistors as the future of classical metal-oxide-semiconductor field effect transistors,” Nature, vol. 479, pp. 310-316, 2011.
[5] P Razavi and A.A. Orouji, “Dual material gate oxide stack symmetric double gate MOSFET: Improving short channel effects of nanoscale double gate MOSFET,” International Biennial Baltic Electronics Conference, pp. 83-86, Tallinn, Estonia, October 6-8, 2008.
[6] S. Mohammadi, A. Afzali-Kusha and S. Mohammadi, “Compact modeling of short-channel effects in symmetric and asymmetric 3-T/4-T double gate MOSFETs,” Microelectronics Reliability, vol. 51, pp. 543-549, 2011.
[7] M. Bhartia and A.K. Chatterjee, “Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs,” Journal of Semiconductors, vol. 36, no. 4, pp 0440031-7, 2015.
[8] R. Shankar, G. Kaushal, S. Maheshwaram, S. Dasgupta and S.K. Manhas, “A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers,” IEEE Trans. Device and Materials Reliability, vol. 14, no. 2, pp. 689-697, 2014.
[9] H.A.E. Hamid, J.Roig Guitart and B.Iníguez, “Two-dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1402-1408, 2007.
[10] Y. Taur, X. Liang, W. Wang and H. Lu, “A continuous, analytical drain current model for double-gate MOSFETs,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 107-109, 2004.
[11] A. Oritiz-Conde, F.J.G. Sonchez and J. Muci, “Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs,” Solid-State Electronics, vol. 49, no. 4, pp. 640-647, 2005.
[12] A.S. Roy, J.M. Sallese and C.C. Enz, “A closed-form charge based expression for drain-current in symmetric and asymmetric double gate MOSFET,” Solid-State Electronics, vol. 50, no. 4, pp. 687-693, 2006.
[13] J.P. Duarte, S. Choi, D. Moon, J. Ahn, J. Kim, S. Kim and Y. Choi, “A universal core model for multiple-gate field-effect transistors. part I: charge model,” IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 840-847, 2013.
[14] J. He, F. Liu, J. Zhang, J. Feng, J. Hu, S. Yang and M. Chan, “A carrier-based approach for compact modeling of the long-channel undoped symmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1203-1209, 2007.
[15] S. Mohammadi and A. Afzali-Kusha, “Modeling of drain current, capacitance and transconductance in thin film undoped symmetric DG MOSFETs including quantum effects,” Microelectronics Reliability, vol. 50, pp. 338-345, 2010.
[16] J.P. Duarte, S. Choi, D. Moon, J. Ahn, J. Kim, S. Kim and Y. Choi, “A universal core model for multiple-gate field-effect transistors. part II: drain current model,” IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 848-855, 2013.
[17] M. Gholizadeh and S.E. Hosseini, “A 2-D analytical model for double-gate tunnel FETs,” IEEE Trans. Electron Devices, vol. 61, no. 5, pp.1494-1500, 2014.
[18] J.P. Duarte, S.J. Choi and Y.K. Choi, “A full-range drain current model for double-gate junctionless transistors,” IEEE Trans. Electron Devices, vol. 58, no. 12, pp. 4219-4225, 2011.
[19] A. Yesayan, F. Jazaeri and J.M. Sallese, “Charge-based modeling of double-gate and nanowire junctionless FETs including interface-trapped charges,” IEEE Trans. Electron Devices, vol. 63, no. 3, pp.1368-1374, 2016.
[20] X. Jin, X. Liu, M. Wu, R. Chuai and J. Lee, “A unified analytical continuous current model applicable to accumulation mode (junctionless) and inversion mode MOSFETs with symmetric and asymmetric double-gate structures,” Solid-State Electronics, vol. 79, pp. 206-209, 2013.
[21] R.K. Baruah and P.P. Roy, “A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor,” Journal of Computational Electronics, vol. 15, no. 1, pp. 45-52, 2016.
[22] C. Jiang, R. Liang, J. Wang and J. Xu, “A two-dimensional analytical model for short channel junctionless double-gate MOSFETs,” AIP Advances, vol. 5, pp. 057122-13, 2015.
[23] T.A. Oproglidis, A. Tsormpatzoglou, D. Tassis, T.A. Karatsori, S. Barraud, G. Ghibaudo and C.A. Dimitriadis, “Analytical drain current compact model in the depletion operation region of short-channel triple-gate junctionless transistors,” IEEE Trans. Electron Devices, vol. 64, no. 1, pp. 66-72, 2017.
[24] F. Ávila-Herrera, B.C. Paz, A. Cerdeira, M. Estrada and M.A. Pavanello, “Charge-based compact analytical model for triple-gate junctionless nanowire transistors,” Solid-State Electronics, vol. 122, pp. 23-31, 2016.
[25] H.C. Pao and C.T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9, no. 10, pp. 927-937, 1966.
[26] D. Munteanu, J. Autran and M. Moreau, “Quantum compact model of drain current in independent double-gate metal-oxide-semiconductor field-effect transistors,” Japanese Journal of Applied Physics, vol. 50, pp. 3011-3018, 2011.
[27] M. Balaguer, J.B. Roldan, L. Donetti and F. Gamiz, “Inversion charge modeling in n-type and p-type double-gate MOSFETs including quantum effects: The role of crystallographic orientation,” Solid-State Electronics, vol. 67, no. 1, pp. 30-37, 2012.
[28] S. Shee, G. Bhattacharyya and S.K. Sarkar, “Quantum analytical modeling for device parameters and I-V characteristics of nanoscale dual-material double-gate silicon-on-nothing MOSFET,” IEEE Trans. Electron Devices, vol. 61, no.8, pp. 2697-2704, 2014.
[29] R. Hosseini, M. Fathipour and R. Faez, “Quantum simulation study of gate-all-around (GAA) silicon nanowire transistor and double gate metal oxide semiconductor field effect transistor (DG MOSFET),” International Journal of the Physical Sciences, vol. 7, no.28, pp. 5054-5061, 2012.
[30] Silvaco. Inc., ATLAS user’s manual, Santa Clara, USA, 2005.