نوع مقاله : علمی-پژوهشی
نویسندگان
1 گروه مهندسی برق دانشگاه فردوسی مشهد
2 گروه مهندسی برق دانشکده مهندسی دانشگاه صنعتی قوچان
چکیده
کلیدواژهها
موضوعات
عنوان مقاله [English]
نویسندگان [English]
In more advanced technologies where the supply voltage is smaller, "half-select problem" becomes more pronounced in SRAM cells. To alleviate this problem without imposing extra power consumption and area, in this paper, a single-ended 10-T structures is proposed. The proposed structure suits low-power applications and because of the cross-point structure, the bit interleaving architecture is allowed to achieve soft error immunity. Since no output node floats during read and write operation, the proposed structure is suitable for working in low operating voltage and high precision circuits. Simulations of a 0.6-V 5-MHz 1-kb SRAM array, confirm that in a 65-nm CMOS technology, the energy required to write a “0” in the single-ended scheme is 53 aJ/kb.
کلیدواژهها [English]
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