Offset Cancellation in a 800MS/s Single-Stage Comparator by Analog Trimming on the Body Voltage of PMOS Devices

Document Type : Original Article

Authors

1 Faculty of Electrical Engineering, Urmia University of Technology, Urmia, Iran

2 Department of Microelectronics Engineering, Urumi Graduate Institute, Urmia, Iran

Abstract

A novel methodology is proposed for offset cancellation in single-stage latched comparators at high comparison speeds. In contrast to the regular methods, high-gain op-amp is not required and the loop accuracy is enhanced by small variations on the body voltages of PMOS devices. Hence, the number of digital signals which are transferred to the analog section are reduced and digital coupling effects are considerably improved. A novel read-out circuit is also proposed which compensates the parasitic capacitance of the next cell and quadruples the fan-out of the comparator, consequently. Worst-Case simulation results confirms that the proposed comparator can detect 1.5mVolts input difference, at all process corners, in presence of 15mVolts input offset voltage, at 800MS/s comparison rate. The Monte-Carlo analysis for 100 iterations on input offset voltages shows that input referred offset would be improved to 150μV while was 25mVolts at 3σ before the correction. Power consumption is 0.55mW at 800MS/s comparison speed. Post-Layout simulation results are presented using the BSIM3v3 model of a 0.18μm CMOS technology.

Keywords

References

[1] مهدی حسین‌نژاد و حسین شمسی، «طراحی و شبیه‌سازی مبدل آنالوگ به دیجیتال لوله‌ای مبتنی بر مقایسه‌گر ولتاژ پایین»، مجله مهندسی برق دانشگاه تبریز، جلد46، شماره1، صفحه87-98 بهار 1395.
[2] A. Couto-Pinto, J. R. Fernandes, M. Piedade and M. Silva, “A Flash ADC Tolerant to High Offset Voltage Comparators”, Circuits, Systems, and Signal Processing, Springer, Vol. 36, Issue. 3, pp: 1150-1168, March2017.
[3] S. Babayan-Mashhadi and R. Lotfi, “An offset cancellation technique for comparators using body-voltage trimming”, Analog Integrated Circuits and Signal Processing, Springer, Vol. 73, Issue. 3, pp: 673-682, December 2012.
[4] Z. Zhu, G. Yu, H, Wu, Y, Zhang and Y. Yang, “A high-speed latched comparator with low offset voltage and low dissipation”, Analog Integrated Circuits and Signal Processing, Springer, Vol. 74, Issue. 2, pp: 467-471, February 2013.
[5] B. Murmann, B-E. Boser, ‘A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification’, IEEE Journal of Solid-State Circuits, Vol.38, No.12, pp.2040-2050, December 2003.
[6] A. J. Ginés, E. Peralías and A. Rueda, “Background Digital Calibration of Comparator Offsets in Pipeline ADCs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 7, pp. 1345-1349, July 2015.
[7] C. Wulff and T. Ytterdal, “Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation”, Analog Integrated Circuits and Signal Processing, Springer, Vol. 67, No.1, pp: 31-40, April 2011.
[8] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure”, IEEE Journal of Solid-State Circuits, Vol. 45, No. 4, pp.731–740, April 2010.
[9] Y. L. Wong, M. H. Cohen and P. A. A Abshire, “A 1.2-GHz comparator with adaptable offset in 0.35-μm CMOS”, IEEE Transactions on Circuits and Systems, Vol. 55, No 9, pp. 2584–2594, October 2008.
[10] B. Han, Y. Yang, Z. Zhu, “A novel 1.2GSPS ultra high-speed comparator in 0.18μm CMOS”, 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008. pp: 1957-1960, 2008.
[11] S. Kazeminia, M. Mousazadeh, Kh. Hadidi and A. Khoei, “A 500MS/s 600μW 300μm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35μm 3.3V CMOS Process”, IEICE Transactions on Electronics, Vol. E94-C, No.4, pages: 635-640, April 2011.
[12] T. Sundstrom and A. Alvandpour, “A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process”, 14th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2007, Pages: 195-198, 2007.
[13] S. Kazeminia and S. Mahdavi, “A 800MS/s, 150µV input-referred offset single-stage latched comparator”, 23rd International Conference on Mixed design of Integrated Circuits and Systems, June 2016, Lodz, Poland, pp: 119-123, MIXDES2016.
[14] Y. Jung, S. Lee, J. Chae and G.C. Temes, “Low-power and low-offset comparator using latch load”, Electronic Letters, vol. 47, Issue. 3, pp. 167-168, February 2011.
[15] Xu Yongsheng, L. Belostotski, and J.W. Haslett, “Offset-Corrected 5GHz CMOS Dynamic Comparator using Bulk Voltage Trimming: Design and Analysis”, IEEE 9th International New Circuits and Systems Conference (NEWCAS), pp. 277-280, June 2011.
[16] D.-S. Khosrov, “A new offset cancelled latch comparator for high-speed, low-power ADCs”, IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, pp: 13-16, 2010.
[17] E. Mikkola, B. Vermeire, H. J. Barnaby, H. G. Parks and K. Borhani, “SET Tolerant CMOS Comparator”, IEEE Transaction on Nuclear Science, Vol. 51, No. 6, pp. 3609-3614, December 2004.
[18] S. Sheikhaei, Sh. Mirabbasi, A. Ivanov, “A 43mW Single-Channel 4GSIs 4-Bit Flash ADC in O.18µm CMOS”, IEEE International Custom Intergrated Circuits Conference (CICC), pp. 333-336, 2007.
[19] Behzad Razavi, “Desigh of Analog CMOS Integrated Circuit”, McGraw-Hill, 2001.
[20] M. Pelgrom and etc, “Matching Properties of MOS Transistors”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989.
[21] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9 μw 4.4 fJ/conversion-step 10 b 1 MS/S charge-redistribution ADC,” in Proceedings of the IEEE International Solid State Circuits Conference (ISSCC '08), pp. 237–610, San Francisco, Calif, USA, February 2008.
[22] J. Craninckx and G. van der Plas, “A 65fJ/conversion-step 0-to-50MS/s 0to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS,” ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007.
[23] A. Khorami and M. Sharifkhani, “High-speed low-power comparator for analog to digital converters”, International Journal of Electronics and Communications (AEÜ) Elsevier, Volume 70, Issue 7, Pages 886-894, July 2016.
[24] S. Rahmani and M. B. Ghaznavi-Ghoushchi, “Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping”, Analog Integrated Circuits and Signal Processing, Springer, Volume 93, Issue 3, pp 507–521, December 2017.
[25] B. Wicht, T. Nirschl and D. S. Landsiedel, “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 7, pp. 1148-1158, July 2004.

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