The integration of random dropout technique with deep recurrent neural networks for modeling the transient behavior of the digital phase-locked loop circuit in the 1 GHz range

Articles in Press

Document Type : Original Article

Authors

1 Department of Electrical Engineering, Yazd University, Yazd, Iran

2 Department of Computer Engineering, Yazd University, Yazd, Iran

Abstract

In this paper, we investigate and model the transient behavior of a digital phase-locked loop (DPLL) clock recovery circuit using artificial neural networks. The circuit modeling in this study is performed using a deep recurrent neural network (RNN), which faced challenges such as overfitting. This issue led to a reduction in the accuracy of the proposed model and a mismatch with real-world data. To address this problem, the dropout technique was employed, which improved the model's performance by reducing its complexity, resulting in a more accurate model compared to the standard deep recurrent neural network models. Additionally, by utilizing a deep gated recurrent unit (GRU), the model error is significantly reduced by 80.32% compared to the Recurrent Neural Network (RNN) model, and the model's accuracy is remarkably improved. The Deep Gated Recurrent Unit not only enhances the model's accuracy but also improves its stability and generalization capability. This method, especially when compared to transistor-level models, provides a model 43.28 times faster, which is important for practical and industrial applications.
compared to the Recurrent Neural Network (RNN) model, and the model's accuracy is remarkably improved. The Deep Gated Recurrent Unit not only enhances the model's accuracy but also improves its stability and generalization capability. This method, especially when compared to transistor-level models, provides a model 43.28 times faster, which is important for practical and industrial applications.

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References

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Tabriz Journal of Electrical Engineering

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