Design of a CNFET-based Quaternary Full Adder

Document Type : Original Article

Authors

Department of Electrical and Computer Engineering, Graduate University of Advanced Technology, Kerman, Iran

Abstract

Full adder cell is an important module in processing systems and has various applications and is used in most arithmetic circuits. Therefore, the design of high-performance Full adder cell will improve the performance of the whole system. On the other hand MOSFET technology has encountered challenges due to the scaling down of transistors. New technologies can be used to solve this problem. Carbon nanotube field effect transistors (CNFETs) are one of the appropriate alternatives to MOSFET. The threshold voltage of these transistors can be easily adjusted by tuning diameter of carbon nanotubes, which makes it very appropriate for designing multi-valued logic circuits. In this paper we have tried to provide a quaternary full adder circuit based on carbon nanotube field effect transistors that is more efficient so that in addition to speeding up the operation, productivity and reducing power consumption are also considered. The proposed design is simulated using the HSPICE Synopsis simulator and compared with previous designs. Simulations have also been performed to investigate the effect of process, temperature and voltage. The results show that the proposed design is faster than previous designs and reduces the PDP parameter by about 75% compared to the best reported design.

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References

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