Design of dynamic frequency phase detector and charge pump with low power consumption in 180nm technology

Document Type : Original Article

Authors

Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, Iran

Abstract

Delay lock loops are widely used in frequency synthesizer circuits, digital transceivers and clock synchronization. Currently, the delay lock ring is considered more than the phase lock ring due to shorter locking time, higher speed, better conditions in terms of stability and less jitter. In this paper, a dynamic phase-frequency detector based on CMOS inverter and multiplexer single with level restoration (MSL) is presented. Next, a new charge pump is proposed that has a precise flow compliance. The charge pump is based on a positive feedback amplifier that has a high gain and at the same time its power consumption has not increased compared to the conventional structure. The simulation results are performed in Cadence software at 0.18 micrometer technology with a supply voltage of 1.8 volts. The simulation results show that the static power consumption of the phase-frequency detector is 0.5 μW and its maximum operating frequency is 2 GHz. Also, the charge pump current matching is about 99.5%.

Keywords

Main Subjects

References

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