طراحی آشکار ساز فاز- فرکانس پویا و پمپ بار با توان مصرفی پاییندر فناوری 180 نانومتر

نوع مقاله : علمی-پژوهشی

نویسندگان

گروه مهندسی برق ، واحد ساری ، دانشگاه آزاد اسلامی ، ساری ، ایران

چکیده

حلقه قفل تأخیر به طور وسیع در مدارات سنتز کننده‌های فرکانس، فرستنده-گیرنده‌های دیجیتالی و همزمان سازی کلاک استفاده می‌شود.در حال حاضر، حلقه قفل تأخیر به علت زمان قفل شدن کمتر، سرعت بالاتر، شرایط بهتر از نظر پایداری و جیتر کمتربیشتر ازحلقه قفل فاز مورد توجه قرار می‌گیرد. در این مقاله، یک آشکارساز فاز-فرکانس پویا مبتنی بر وارونگر CMOS و مالتی پلکسر با ترمیم سطحMSL) ) ارائه می‌شود. در ادامه، یک پمپ بار جدید پیشنهاد می‌شود که تطابق جریانی دقیقی دارد. پمپ بار مبتنی بر تقویت‌کننده با فیدبک مثبت است که بهره بالایی دارد و در عین حال توان مصرفی آن نسبت به ساختار مرسوم افزایش نیافته است. نتایج شبیه‌سازی درفناوری18/0میکرومتر و با ولتاژ تغذیه 8/1 ولت توسط نرم‌افزار Cadence انجام می‌شود. نتایج شبیه‌سازی نشان می‌دهد که مقدار توان مصرفی استاتیک آشکارساز فاز-فرکانس برابر 5/0 میکرو وات و حداکثر فرکانس کاری آن ۲ گیگاهرتز است. هم‌چنین، تطابق جریانی پمپ بارحدود 5/99 درصد است .

کلیدواژه‌ها

موضوعات

عنوان مقاله [English]

Design of dynamic frequency phase detector and charge pump with low power consumption in 180nm technology

نویسندگان [English]

  • F. EsmailiSaraji
  • A. Ghorbani
  • S. M. Anisheh
Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, Iran
چکیده [English]

Delay lock loops are widely used in frequency synthesizer circuits, digital transceivers and clock synchronization. Currently, the delay lock ring is considered more than the phase lock ring due to shorter locking time, higher speed, better conditions in terms of stability and less jitter. In this paper, a dynamic phase-frequency detector based on CMOS inverter and multiplexer single with level restoration (MSL) is presented. Next, a new charge pump is proposed that has a precise flow compliance. The charge pump is based on a positive feedback amplifier that has a high gain and at the same time its power consumption has not increased compared to the conventional structure. The simulation results are performed in Cadence software at 0.18 micrometer technology with a supply voltage of 1.8 volts. The simulation results show that the static power consumption of the phase-frequency detector is 0.5 μW and its maximum operating frequency is 2 GHz. Also, the charge pump current matching is about 99.5%.

کلیدواژه‌ها [English]

  • Frequency synthesizers
  • Delay lock loop
  • Dynamic frequency-phase detector
  • Load pump
  • Low power consumption

مراجع

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