Design and Evaluation of a Carry-Skip Adder in Quantum Cellular Automata Technology

Document Type : Original Article

Authors

1 Department of Computer Engineering, North Tehran Branch, Islamic Azad University, Tehran, Iran

2 Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran

Abstract

Adders are among the most practical and useful circuits in microprocessors. They could also be used in other arithmetic operators. Traditionally, they are fabricated using CMOS technology. However, CMOS has faced some challenges in the nanoscale regime such as reduced gate controllability and high leakage currents. In contrast, Quantum Cellular Automata (QCA) is a promising alternative for the challenges of the next generation digital circuits. Based on QCA idea, in this paper a Carry-Skip Adder (CSA) is designed, which as far as investigated, has not been previously presented in related works. As CSA adders are generally faster than ripple ones, our simulation results also confirm that the proposed CSA outperforms the state-of-the-art ripple and carry lookahead adders and produces the result three QCA clock cycles faster even in the worst-case scenario. In addition, the proposed QCA adder outperforms its CMOS counterpart in terms of speed and power consumption.

Keywords


[1]      A. M. Shams and M. Bayoumi, “Performance evaluation of 1-bit CMOS adder cell,” Proceedings of the IEEE International Symposium on Circuits and Systems VLSI, pp. 27-30, May 1999.
[2]      S. Mehrabi, R. Faghih Mirzaee, S. Zamanzadeh and A. Jamalian, “Multiplication with m:2 and m:3 compressors: A comparative review,” Canadian Journal of Electrical and Computer Engineering, vol. 40, no. 4, pp. 303-313, 2017.
[3]      G. B. Rosenberger, Simultaneous carry adder, U.S. Patent 2,966,305, 1960.
[4]      B. Parhami, Computer Arithmetic: Algorithms and Hardware Design. Part II, Oxford University Press, 2000.
[5]      M. Alioto and G. Palumbo, “A simple strategy for optimized design of one-level carry-skip adders,” IEEE Transactions on Circuits and Systems I, vol. 50, no. 1, pp. 141-148, 2003.
[6]      Y. -B. Kim, “Challenges for nanoscale MOSFETs and emerging nanoelectronics,” Transactions on Electrical and Electronic Materials, vol. 11, no. 3, pp. 93-105, 2010.
[7]      R. Martel, T. Schmidt, H. R. Shea, T. Hertel and P. Avouris, “Single- and multi-wall carbon nanotube field-effect transistors,” Applied Physics Letters, vol. 73, no. 17, pp. 2447-2449, 1998.
[8]      K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B. J. Vartanian and J.S. Harris, “Room temperature operation of a single electron transistor made by the scanning tunneling microscope nanooxidation process for the TiOx/Ti system,” Applied Physics Letters, vol. 68, no. 1, pp. 34-36, 1995.
[9]      C. S. Lent, P. D. Tougaw, W. Porod and G. H. Bernstein “Quantum cellular automata,” Nanotechnology, vol. 4, pp. 49-57, 1993.
[10]      D. A. Reis, C. A. T. Campos, T. R. B. S. Soares, O. P. V. Neto and F. S. Torres, “A methodology for standard cell design for QCA,” IEEE International Symposium on Circuits and Systems, pp. 2114-2117, May 2016.
[11]      K. Kim, K. Wu and R. Karri, “Quantum-dot cellular automata design guideline,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, vol. E89-A, no. 6, pp. 1607-1614, 2006.
[12]      W. Lin, E. E. Swartzlander Jr. and M. O’Neill, Design of semiconductor QCA systems. Part II, Artech House, 2013.
[13]      T. N. Sasamal, A. K. Singh and U. Ghanekar, “Efficient design of coplanar ripple carry adder in QCA,” IET Circuits, Devices & Systems, vol. 12, no. 5, pp. 594-605, 2018.
[14]      M. Mahad and M. Waje, “Implementation of ripple carry adder using advanced multilayer three input XOR gate (TIEO) technique in QCA technology,” International Journal of Electronics and Communication Engineering and Technology, vol. 8, no. 4, pp. 60-67, 2017.
[15]      M. Mohammadi, M. Mohammadi and S. Gorgin, “An efficient design of full adder in quantum-dot cellular automata,” Microelectronics Journal, vol. 50, pp. 35-43, 2016.
[16]      D. Abedi, G. Jaberipur and M. Sangsefidi, “Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover,” IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 497-504, 2015.
[17]      S. Perri, P. Corsonello and G. Cocorullo, “Area-delay efficient binary adders in QCA,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1174-1179, 2014.
[18]      V. Pudi and K. Sridharan, “Low complexity design of ripple carry and Brent-Kung adders in QCA,” IEEE Transactions on Nanotechnology, vol. 11, no. 1, pp. 105-119, 2012.
[19]      V. Pudi and K. Sridharan, “New decomposition theorems on majority logic for low-delay adder designs in quantum dot cellular automata,” IEEE Transactions on Circuits and Systems II, vol. 59, no. 10, pp. 678-682, 2012.
[20]      M. Macucci, G. Iannaccone, S. Francaviglia and B. Pellegrini, “Semiclassical simulation of quantum cellular automaton circuits,” International Journal of Circuits Theory and Applications, vol. 29, no. 1, pp. 37-47, 2001.
[21]      C. S. Lent and P.D. Tougaw, “A device architecture for computing with quantum dots,” Proceedings of IEEE, vol. 85, no. 4, pp. 541-541, 1997.
[22]      C. Labrado and H. Thapliyal, “Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing,” Electronics Letters, vol. 52, no. 6, pp. 464-466, 2016.
[23]      J. C. Das and D. De, “Optimized multiplexer design and simulation using quantum dot-cellular automata,” Indian Journal of Pure & Applied Physics, vol. 54, pp. 802-811, 2016.
[24]      R. Zhang, P. Gupta and N. K. Jha, “Majority and minority network synthesis with application to QCA-, SET-, and TPL-based nanotechnologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 7, pp. 1233-1245, 2007.
[25]      T. N. Sasamal, A. K. Singh and U. Ghanekar, “Design of non-restoring binary array divider in majority logic-based QCA,” Electronics Letters, vol. 52, no. 24, pp. 2001-2003, 2016.
[26]      P. Verma, S. Jaishwal and S. Rathora, “Design of high-speed and low power carry skip adder,” International Journal of Advanced Research in Computer and Communication Engineering, vol. 6, no. 11, pp. 272-275, 2017.