Four-port non-blocking switch for reducing insertion loss in hybrid photonic networks-on-chip

Document Type : Original Article

Authors

1 Department of Computer Engineering, Science and Research Branch Islamic Azad University, Tehran, Iran

2 Iran Telecommunication Research Center, ITRC, Tehran, Iran,

3 Department of Computer Engineering, Shahr-e-Qods Branch Islamic Azad University, Tehran, Iran,

Abstract

A multi-processor architecture was proposed to address power consumption limitations in chips in order to increase performance and lower power consumption. In this architecture, the highest power consumption comes from the chip connections. Optical connections can reduce power consumption and increase performance via a new architecture called photonic network-on-chips, which are capable of utilizing the benefits of optical signals and elements for data transfer. This paper proposes a 4×4, non-blocking photonic switch to improve physical layer parameters by increasing photonic network performance. The insertion loss and energy dissipation of the proposed switch were compared to three switches: Original, StraightPath, and Symmetric switches. The results indicated that, in a mesh topology, the proposed switch reduced loss for the GTC, Cactus, Tornado, and MADbench by 28.22, 24.46, 28.72, and 29.20%, respectively, when compared to the Original switch. According to PhoenixSim simulation results, the proposed switch reduced insertion loss and energy dissipation in photonic network-on-chips when compared to the three comparison switches.

Keywords

References

[1]      G. De Micheli and L. Benini, Networks on chips: technology and tools. Academic Press, 2006.
[2]      رضا تقی‌زاده و محمدعلی جبرئیل جمالی، «مسیریاب غیروفقی شبکه بر تراشه باقابلیت هم‌زمان تحمل‌پذیری خرابی و آزمایش برخط اتصالات بین مسیریاب‌ها» مجله مهندسی برق دانشگاه تبریز، دوره 47، شماره 4، صفحه  1406-1395، زمستان 1396.
[3]      A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” Computers, IEEE Transactions on, vol. 57, no. 9, pp. 1246-1260, 2008.
[4]      J. W. Goodman, F. I. Leonberger, S.-Y. Kung, and R. A. Athale, “Optical interconnections for VLSI systems,” Proceedings of the IEEE, vol. 72, no. 7, pp. 850-866, 1984.
[5]      A. Shacham, B. G. Lee, A. Biberman, K. Bergman, and L. P. Carloni, “Photonic NoC for DMA communications in chip multiprocessors,” in High-Performance Interconnects, 2007. HOTI 2007. 15th Annual IEEE Symposium on, 2007, pp. 29-38: IEEE.
[6]      R. A. Soref and J. P. Lorenzo, “All-silicon active and passive guided-wave components for lambda= 1.3 and 1.6 microns,” IEEE Journal of Quantum Electronics, vol. 22, pp. 873-879, 1986.
[7]      D. A. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proceedings of the IEEE, vol. 88, no. 6, pp. 728-749, 2000.
[8]      A. Dhiman, “Silicon photonics: a review,” IOSR J. Appl. Phys, vol. 3, pp. 67-79.
[9]      S. Werner, J. Navaridas, and M. Lujأ،n, “A Survey on Optical Network-on-Chip Architectures,” ACM Computing Surveys (CSUR), vol. 50, pp. 89.
[10]      R. Syms and J. Cozens, “Optical guided waves and devices. 1992,” ed: McGraw-Hill.
[11]      اشکان قنبری، علی صدر و مهران نیکو، «بیشینه‌سازی ضریب فشردگی و پهنای باند پالس‌های نوری با استفاده از چرپ فرکانسی در فیبرهای فوتونیک کریستال» مجله مهندسی برق دانشگاه تبریز، دوره 43، شماره 2، صفحه  42-31، پاییز  1392.
[12]      M. Lipson, “Guiding, modulating, and emitting light on silicon-challenges and opportunities,” Lightwave Technology, Journal of, vol. 23, no. 12, pp. 4222-4238, 2005.
[13]      H. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” in Proceedings of the conference on Design, Automation and Test in Europe, 2009, pp. 3-8: European Design and Automation Association.
[14]      P. Koonath, T. Indukuri, and B. Jalali, “Add-drop filters utilizing vertically coupled microdisk resonators in silicon,” Applied Physics Letters, vol. 86, no. 9, p. 091102, 2005.
[15]      B. G. Lee, A. Biberman, N. Sherwood-Droz, C. B. Poitras, M. Lipson, and K. Bergman, “High-Speed 2$, times, $2 Switch for Multiwavelength Silicon-Photonic Networks–On-Chip,” Journal of Lightwave Technology, vol. 27, no. 14, pp. 2900-2907, 2009.
[16]      K. M. İmre, “Dual-mode routing approach for photonic network on chip platforms,” The Journal of Supercomputing, vol. 72, no. 3, pp. 904-925, 2016.
[17]      H. Wang, M. Petracca, A. Biberman, B. G. Lee, L. P. Carloni, and K. Bergman, “Nanophotonic optical interconnection network architecture for on-chip and off-chip communications,” in Optical Fiber Communication Conference, 2008, p. JThA92: Optical Society of America.
[18]      Z. Chang, J. Tang, and Y. Jin, “An insertion loss balance aware routing scheme in photonic network on chip,” in Information, Communications and Signal Processing, 2009. ICICS 2009. 7th International Conference on, 2009, pp. 1-5: IEEE.
[19]      A. Shacham, K. Bergman, and L. P. Carloni, “On the design of a photonic network-on-chip,” in Proceedings of the First International Symposium on Networks-on-Chip, 2007, pp. 53-64: IEEE Computer Society.
[20]      J. Chan, A. Biberman, B. G. Lee, and K. Bergman, “Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications,” IEEE Lasers and Electro-Optics Society (LEOS), 2008.
[21]      M. J. Cianchetti and D. H. Albonesi, “A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 7, no. 2, p. 9, 2011.
[22]      H. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” in VLSI, 2009. ISVLSI'09. IEEE Computer Society Annual Symposium on, 2009, pp. 19-24: IEEE.
[23]      A. B. Ahmed and A. B. Abdallah, “Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems,” The Journal of Supercomputing, vol. 71, no. 12, pp. 4446-4475, 2015.
[24]      Y. Ye, J. Xu, X. Wu, W. Zhang, W. Liu, M. Nikdast, X. Wang, Z. Wang, and Z. Wang, “Thermal analysis for 3D optical network-on-chip based on a novel low-cost 6× 6 optical router,” in Optical Interconnects Conference, 2012 IEEE, 2012, pp. 110-111: IEEE.
[25]      A. W. Poon, F. Xu, and X. Luo, “Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip,” presented at Integrated Optoelectronic Devices 2008, 2008.
[26]      A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE, vol. 97, pp. 1216-1238, 2009.
[27]      P. Guo, W. Hou, L. Guo, Q. Yang, Y. Ge, and H. Liang, “Low Insertion Loss and Non-Blocking Microring-Based Optical Router for 3D Optical Network-on-Chip,” IEEE Photonics Journal, vol. 10, pp. 1-10.
[28]      L. Guo, W. Hou, and P. Guo, “Designs of 3D mesh and torus optical Network-on-Chips: Topology, optical router and routing module,” China Communications, vol. 14, pp. 17-29.
[29]      J. Chan, G. Hendry, K. Bergman, and L. P. Carloni, “Physical-layer modeling and system-level design of chip-scale photonic interconnection networks,” IEEE Transactions on computer-aided design of integrated circuits and systems, vol. 30, no. 10, pp. 1507-1520, 2011.
[30]      F. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nature photonics, vol. 1, no. 1, pp. 65-71, 2007.
[31]      W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides,” Optics letters, vol. 32, no. 19, pp. 2801-2803, 2007.
[32]      B. G. Lee, A. Biberman, P. Dong, M. Lipson, and K. Bergman, “All-optical comb switch for multiwavelength message routing in silicon photonic networks,” IEEE Photonics Technology Letters, vol. 20, no. 10, pp. 767-769, 2008.
[33]      K. Bergman, L. P. Carloni, A. Biberman, J. Chan, and G. Hendry, Photonic Network-on-Chip Design. Springer, 2014.
[34]      H. Wang, M. Petracca, A. Biberman, B. G. Lee, L. P. Carloni, and K. Bergman, “Nanophotonic optical interconnection network architecture for on-chip and off-chip communications,” presented at Optical Fiber Communication Conference, 2008.
[35]      J. Chan, G. Hendry, A. Biberman, K. Bergman, and L. P. Carloni, “Phoenixsim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks,” in Proceedings of the Conference on Design, Automation and Test in Europe, 2010, pp. 691-696: European Design and Automation Association.
[36]      G. Hendry and J. Chan, “PhoenixSim 1.0 User Manual,” Lightwave Research Lab, Columbia Univ., New York, NY, USA, 2011.
[37]      A. Varga and R. Hornig, “An overview of the OMNeT++ simulation environment,” in Proceedings of the 1st international conference on Simulation tools and techniques for communications, networks and systems & workshops, 2008, p. 60: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering).
[38]      A. Varga, “The OMNeT++ discrete event simulation system,” in Proceedings of the European simulation multiconference (ESM’2001), 2001, vol. 9, no. S 185, p. 65: sn.
[39]      N. E. Jerger and L.-S. Peh, On-chip networks, Synthesis Lectures on Computer Architecture, vol. 4, no. 1, pp. 1-141, 2009.
[40]      J. Chan and K. Bergman, “Photonic interconnection network architectures using wavelength-selective spatial routing for chip-scale communications,” Journal of Optical Communications and Networking, vol. 4, no. 3, pp. 189-201, 2012.
[41]      L. Liu and Y. Yang, “Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip,” Journal of Parallel and Distributed Computing, vol. 73, no. 2, pp. 189-197, 2013.
[42]      M. R. Watts, D. C. Trotter, R. W. Young, and A. L. Lentine, “Ultralow power silicon microdisk modulators and switches,” in 5th Annual Conference on Group IV Photonics, 2008, pp. 4-6.
[43]      G. Hendry, S. Kamil, A. Biberman, J. Chan, B. G. Lee, M. Mohiyuddin, A. Jain, K. Bergman, L. P. Carloni, and J. Kubiatowicz, “Analysis of photonic networks for a chip multiprocessor using scientific applications,” in Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on, 2009, pp. 104-113: IEEE.
[44]      Z. Lin, S. Ethier, T. Hahm, and W. Tang, “Size scaling of turbulent transport in magnetically confined plasmas,” Physical Review Letters, vol. 88, no. 19, p. 195004, 2002.
[45]      Cactus Computational Toolkit [Online]. Available: http://www.cactuscode.org/.
[46]      J. Borrill, J. Carter, L. Oliker, D. Skinner, and R. Biswas, “Integrated performance monitoring of a cosmology application on leading HEC platforms,” in 2005 International Conference on Parallel Processing (ICPP'05), 2005, pp. 119-128: IEEE.
TABRIZ JOURNAL OF ELECTRICAL ENGINEERING
Volume 50, Issue 3 - Serial Number 93
November 2020
Pages 1193-1204

Files

Share

How to cite

Statistics