Optical Clock Distribution Network using CMOS Single-photon Avalanche Diodes

Document Type : Original Article

Authors

Department of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran

Abstract

A new clock distribution network using CMOS single-photon avalanche diodes (SPAD) in combination with free space optics is proposed. The system can work without special implementation of optical waveguides. It consists of an optical source with 660 MHz operation, which in the receiver end is composed of three parallel SPADs biased in quench, hold-off and recharge phases. With the pipeline analogues implementation of SPADs and a logic cell output a 660 MHz clock source can be achieved. The proposed system is post layout simulated in 180nm CMOS technology. The power consumption of 6.74 mW for each SPAD cell, electrical jitter of 237 fs and skew of 43 ps is resulted.

Keywords


[1]      C. Thangaraj, R. Pownall, P. Nikkel, G. Yuan, K. L. Lear, and T. Chen, “Fully CMOS-compatible on-chip optical clock distribution and recovery,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 10, pp. 1385-1398, 2010.
[2]      J. Warnock, B. Curran, J. Badar, G. Fredeman, D. Plass, Y. Chan, S. Carey, G. Salem, F. Schroeder, and F. Malgioglio, "4.1 22nm Next-generation IBM System z microprocessor.", Solid-State Circuits Conference-(ISSCC), pp. 1-3, 2015.
[3]      N. H. E. Weste, and D. Harris, " Sequential Circuit Design," CMOS VLSI design: A circuits and systems perspectives, Boston: Addison Wesley, 2005.
[4]      B. Ackland, B. Razavi, and L. West, "A comparison of electrical and optical clock networks in nanometer technologies", Custom Integrated Circuits Conference, pp. 779-782, 2005.
[5]      C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, and D. A. Miller, “Receiver-less optical clock injection for clock distribution networks,” Selected Topics in Quantum Electronics, IEEE Journal of, vol. 9, no. 2, pp. 400-409, 2003.
[6]      D. Pham, S. Asano, M. Bolliger, M. N. Day, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, and K. Yazawa, "The design and implementation of a first-generation CELL processor - a multi-core SoC.", Digest of Technical Papers. ISSCC,pp. 49-52, 2005.
[7]      P. Mahoney, E. Fetzer, B. Doyle, and S. Naffziger, "Clock distribution on a dual-core, multi-threaded Itanium®-family processor.", Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC, pp. 292-599, 2005.
[8]      C. C. Tsai, C. C. Kuo, F. T. Hsu, L. J. Gu, and T. Y. Lee, "X-architecture zero-skew clock tree construction with performance and DFM considerations.", SoC Design Conference (ISOCC), 2010 International, pp. 294-297, 2010.
[9]      W. K. Loo, K. S. Tan, and Y. K. Teh, "A study and design of CMOS H-Tree clock distribution network in system-on-chip.", ASIC, 2009. ASICON'09. IEEE 8th International Conference, pp. 411-414, 2009.
[10]      C. Hongyu, C. Chung-Kuan, A. B. Kahng, I. I. Mandoiu, W. Qinke, and Y. Bo, “The Y architecture for on-chip interconnect: analysis and methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 588-599, 2005.
[11]      A. V. Mule, E. N. Glytsis, T. K. Gaylord, and J. D. Meindl, “Electrical and optical clock distribution networks for gigascale microprocessors,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 10, no. 5, pp. 582-594, 2002.
[12]      C. Favi, T. Kluter, C. Mester, and E. Charbon, “Optically-clocked instruction set extensions for high efficiency embedded processors,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, no. 3, pp. 604-615, 2012.
[13]      Y. Zhang, X. Xu, D. Kwong, J. Covey, A. Hosseini, and R. T. Chen, “0.88-THz Optical Clock Distribution on Adhesively Bonded Silicon Nanomembrane,” Photonics Technology Letters, IEEE, vol. 26, no. 23, pp. 2376-2379, 2014.
[14]      B. Krueger ,R. E.  Makon, O. Landolt ,O.  Hidri, T. Schweiger, E. Krune, D. Knoll, S. Lischke, and J. Schulze. “A monolithically integrated, optically clocked 10 GS/s sampler with a bandwidth of> 30 GHz and a jitter of< 30 fs in photonic SiGe BiCMOS technology.“ IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, IEEE, 2017.
[15]      C. Favi, “Single-photon techniques for standard CMOS digital ICs,” PhD thesis, EPFL, 2011.
[16]      M. A. Karami, “Deep-submicron CMOS single photon detectors and quantum effects,” PhD thesis, TU Delft, Delft University of Technology, 2011.
[17]      M. J. Lee, M. R. Ximenes, P. Padmanabhan, T. J. Wang, K. C. Huang, Y. Yamashita, D. N. Yaung, and E. Charbon, “A back illuminated 3D- stacked single-photon avalanche diode in 45nm CMOS technology”, IEEE Electron Device Meeting (IEDM), pp. 6-16, 2017.
[18]      T. C. de Albuquerque, F. Calmon, R. Clerc, P. Pittet, Y. Benhammou, D. Golanski, S. Juan, D. Rideau, A. Cathelin, “Integration of SPAD in 28nm FDSOI CMOS technology”, 48th European solid-state device research conference (ESSDERC), 2018.
[19]      D. Mora, A. Tosi, S. Tisa, and F. Zappa, “Single-photon avalanche diode model for circuit simulations,” Photonics Technology Letters, IEEE, vol. 19, no. 23, pp. 1922-1924, 2007.
[20]      D. Palubiak, M. M. El-Desouki, O. Marinov, M. J. Deen, and Q. Fang, “High-speed, single-photon avalanche-photodiode imager for biomedical applications,” Sensors Journal, IEEE, vol. 11, no. 10, pp. 2401-2412, 2011.
[21]      M. Liu, C. Hu, J. C. Campbell, Z. Pan, and M. M. Tashima, "A novel quenching circuit to reduce afterpulsing of single photon avalanche diodes.", Quantum Sensing and Nanophotonic Devices, pp. 69001F, 2009.
[22]      M. A. Wayne, A. Restelli, J. C. Bienfang, and P. G. Kwiat, “Afterpulse Reduction Through Prompt Quenching in Silicon Reach-Through Single-Photon Avalanche Diodes,” Journal of Lightwave Technology, vol. 32, no. 21, pp. 3495-3501, 2014.
[23]      A. Gallivanoni, I. Rech, and M. Ghioni, “Progress in quenching circuits for single photon avalanche diodes,” IEEE Transactions on Nuclear Science, vol. 57, no. 6, pp. 3815-3826, 2010.
[24]      C. Niclass, and M. Soga, "A miniature actively recharged single-photon detector free of afterpulsing effects with 6ns dead time in a 0.18µm CMOS technology”, Electron Devices Meeting (IEDM), 2010.
[25]      D. Bronzi, S. Tisa, F. Villa, S. Bellisai, A. Tosi, and F. Zappa, “Fast sensing and quenching of CMOS SPADs for minimal afterpulsing effects,” IEEE Photonics Technology Letters, vol. 25, no. 8, pp. 776-779, 2013.
[26]      M. Gronholm, J. Poikonen, and M. Laiho, "A ring-oscillator-based active quenching and active recharge circuit for single photon avalanche diodes.", European conference, Circuit Theory and Design ECCTD, pp. 5-8, 2009.
[27]      محمد عظیم کرمی، میثاق انصاریان و سوده عقلی مقدم، "نوسان ساز حلقوی جدید کنترل شده با ولتاژ با استفاده از اثر میلر"، مجله مهندسی برق دانشگاه تبریز، جلد 47، شماره 1 صفحه 221-228، 1396.
[28]      C. S. U. s. Manual, “Cadence design systems,” San Jose, CA, 1994.
[29]      خلیل منفردی و یوسف بلقیس آذر "تقویت کننده کسکود تمام تفاضلی بازیابی تا شده بهبود یافته ولتاژو توان پایین"، مجله مهندسی برق دانشگاه تبریز، جلد 48، شماره 1 صفحه 328-334و 1397.
[30]      V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. C. Papaefthymiou, and S. Naffziger, “Resonant-clock design for a power-efficient, high-volume x86-64 microprocessor,” Solid-State Circuits, IEEE Journal of, vol. 48, no. 1, pp. 140-149, 2013.
[31]      P. Restle, D. Shan, D. Hogenmiller, Y. Kim, A. Drake, J. Hibbeler, T. Bucelot, G. Still, K. Jenkins, and J. Friedrich, " Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8 TM microprocessor.”, Solid-State Circuits Conference Digest of Technical Papers, pp. 100-101, 2014.
[32]      S. Rusu, H. Muljono, D. Ayers, S. Tam, W. Chen, A. Martin, S. Li, S. Vora, R. Varada, and E. Wang, " A 22nm 15-core enterprise Xeon® processor family.” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 102-103, 2014.
[33]      J. Stinson, and S. Rusu, " Stinson J, Rusu S. A 1.5 GHz third generation itanium® 2 processor”. Proceedings of the 40th annual Design Automation Conference, ", vol.1, pp. 706-709, 2003.
[34]      S. Rusu, and S. Tam, " Clock generation and distribution for the first IA-64 microprocessor.”, IEEE Journal of Solid-State Circuits, Vol. 35, no.1, pp. 1545-1552, 2000.