A Fully Differential Latched Comparator with a Novel Offset Cancellation Technique

Authors

School of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran

Abstract

A Fully Differential latched comparator using a new offset cancellation technique is presented. The comparator consists of three stages: the input pre-amplifier, a latch stage and the offset cancellation circuitry. The kick-back noise can be significantly reduced by using a pre-amplifier stage. Also, the offset and noise of the latch and offset cancellation stages are attenuated by the gain of the pre-amplifier when referred to the input. Latches regenerate faster than pre-amplifiers and provide a full swing digital output for the comparator. The last stage is the offset cancellation circuitry. The main advantage of the proposed offset cancellation technique is that it does not need to make any interrupt in normal operation of comparator to eliminate offset error. In order to evaluate the performance of the comparator, simulations are performed in a 0.18µm standard CMOS technology. Simulation results show that the offset of the pre-amplifier and latch stages are significantly eliminated by this cancellation technique and only about 450µv offset voltage will be referred to the input. The proposed comparator operates at 500MHz clock frequency and dissipates 373µw from a 1.8v supply. Also, it has a propagation delay of 138ps and kick-back noise of 0.54mv.

Keywords

References

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TABRIZ JOURNAL OF ELECTRICAL ENGINEERING
Volume 48, Issue 4 - Serial Number 86
February 2018
Pages 1831-1842

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