Non-adaptive Router of Network on Chip with Capabilities of Fault Tolerance and Online Test of Interconnections among Routers

Authors

1 Department of Computer Engineering, Tabriz Branch, Islamic Azad University, Tabriz, Iran

2 Department of Computer Engineering, Shabestar Branch, Islamic Azad University, Shabestar, Iran

Abstract

Since providing service quality for critical and real time systems is essential, online test and fault tolerance are considered to be of high significance in designing chips for these systems. The dominant routing algorithm of Network on Chip (NoC) in critical and real time systems is deterministic routing algorithm. Due to the effects of crosstalk, NoC communication infrastructure is highly prone to fault and failure. Thus, effective and efficient testing mechanisms should be designed for detecting faults in the form of both online testing and fault tolerance so that fault tolerance time is minimized. In this paper, a method was proposed for online testing of interconnections among non-adaptive routers with deterministic routing algorithms. Indeed, by embedding a test pattern generator and four comparators in each router and producing interconnection redundancy among routers, the need for stopping usual system operations while testing is obviated. In the proposed architecture, interconnections were tested with chip frequency. As faults and failures are detected, the opportunity for tolerating them is created simultaneously. The results of conduct simulations in this study revealed that the proposed router was able to significantly reduce test execution time with minimum area overhead and power consumption.

Keywords

TABRIZ JOURNAL OF ELECTRICAL ENGINEERING
Volume 47, Issue 4 - Serial Number 82
February 2017
Pages 1395-1406

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