Multiple-Event Soft Error Reduction of Combinational Circuits Using Gate Sizing Based on Sensitivity Parameter

Authors

1 Faculty of Engineering, Shahid Bahonar University of Kerman, Kerman, Iran

2 Faculty of Electrical and Computer Engineering, University of Shiraz, Shiraz, Iran

Abstract

The aggressive device scaling and exponential increase in transistor counts of a chip have increasingly made the modern integrated circuits more susceptible to soft errors. Soft errors are caused by strikes from energetic particles such as neutrons and alpha particles. With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). So in design process of such circuits, optimization techniques are required to be aware of multiple-event transient faults. In this paper, a new framework to improve the tolerability of combinational circuits against METs is provided. In this context, by resizing the sensitive gates, electrical masking of the gates are increased and thus, the Soft Error Rate (SER) of the combinational circuit is improved. The experimental results on ISCAS’85 benchmark circuits show that using the proposed framework, which considers METs, leads to 4X improvement in SER of the circuits compared the original circuit. Also 2X improvement in circuit SER is achieved when only SETs are taken into consideration for gate sizing.

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