School of Engineering, University of Damghan, Damghan, Iran
Abstract
In this paper, a new domino circuit is proposed to reduce power consumption of wide fan-in gates without considerable speed degradation. In the proposed domino circuit technique, current of the pull-down network is compared with a reference current to generate the proper output voltage. In this way, voltage swing of the pull-down network can be decreased to reduce power consumption. Moreover, a transistor in diode configuration is employed in series with the pull-down network to decrease the sub-threshold leakage current and increase the noise immunity. Simulation of wide fan-in OR gates are performed using HSPICE simulator in a 90nm CMOS technology model. Simulation results demonstrate 39% power reduction and 2.1× noise-immunity improvement at the same delay compared to the standard domino circuit for 64-bit OR gates.
Asyaei, M. (2017). Enhanced Current Comparison Based Domino for Design of Low Power Wide Fan-In Gates. TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, 47(1), 1-10.
MLA
M. Asyaei. "Enhanced Current Comparison Based Domino for Design of Low Power Wide Fan-In Gates". TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, 47, 1, 2017, 1-10.
HARVARD
Asyaei, M. (2017). 'Enhanced Current Comparison Based Domino for Design of Low Power Wide Fan-In Gates', TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, 47(1), pp. 1-10.
VANCOUVER
Asyaei, M. Enhanced Current Comparison Based Domino for Design of Low Power Wide Fan-In Gates. TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, 2017; 47(1): 1-10.
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