FPGA Implementation of a Multiplier-Free Ternary RNS Reverse Converter for a new 4-Moduli Set {3^n,3^n-2,3^n+2,3^n-1} Using Binary-Encoded Ternary Logic.

Document Type : Original Article

Authors

1 Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran

2 Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran

Abstract

In this paper, we present a novel FPGA-based implementation of a multiplier-free reverse converter for the residue number system (RNS) using a new 4-moduli set {3^n, 3^n-2, 3^n+2, 3^n-1}. The proposed method leverages the unbalanced ternary logic system to achieve efficient residue-to-binary conversion with reduced computational complexity and hardware resource usage. The core architecture eliminates the need for hardware multipliers by exploiting mathematical simplifications and residue properties inherent to the chosen moduli set. Ternary digits are encoded in binary to enable implementation on conventional FPGA platforms. The design is suitable for high-speed applications. Since no comparable ternary RNS reverse converter exists in the current literature, a baseline method was implemented for evaluation. Simulation and synthesis results confirm the efficiency of the proposed design in terms of area, speed, and power consumption, making it a promising solution for low-power, high-performance signal processing and cryptographic systems.

Keywords

Main Subjects

References

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