Design of Transistor Neuron in 180-nm CMOS Technology for Spiking-Based Neural Networks

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Document Type : Original Article

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Department of Electronics and communication Engineering, Faculty of Engineering, University of Kurdistan, Sanandaj, Iran

Abstract

This paper proposes an analog neuron with the capability of operating under low-voltage supplies. The proposed neuron uses a current-mode low-pass filter with a variable gain to linearly integrate the input spikes onto the membrane capacitance. The spike generator circuit includes a positive feedback loop that not only increases the switching speed but also causes low energy consumption. The use of positive feedback eases the implementation of the frequency adaptation mechanism achieving a realistic time-constant and low power dissipation. An inverter-based voltage comparator is also employed to provide the threshold voltage of the spike generator circuit and re-adjust the membrane potential. Mathematical analyses in the subthreshold region show a first-order linear equation that confirms the structure’s simplicity and linearity of the proposed neuron. The simulation results in the 180-nm CMOS process under a 0.3-V supply voltage report an energy consumption of 176 fJ/spike. In addition, by adjusting the control parameters, the neuron shows different firing patterns such as slow and fast firing, chattering behavior, and frequency adaption mechanism.

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Tabriz Journal of Electrical Engineering

Articles in Press, Corrected Proof
Available Online from 22 September 2025

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