ROBUST AND HIGH-SPEED MTJ/CMOS 5-2 COMPRESSORS

Document Type : Original Article

Authors

Department of Electrical and Computer Engineering, Graduate University of Advanced Technology, Kerman, Iran

Abstract

Compressors are one of the most critical components of multipliers. Thus, improving this part’s energy consumption, delay, and area can directly affect the systems’ overall efficiency. Also, Magnetic tunnel junction (MTJ) devices have been studied as a prosperous solution to implement low-power circuits thanks to their non-volatility, high speed, low power, good endurance, and scalability. This paper uses MTJs to develop two hybrid MTJ/CMOS low-power designs of a 5-2 compressor. The proposed designs are simulated in the HSPICE simulator using 45nm standard CMOS technology and the spin torque transfer (STT) MTJ model. Finally, the new designs compared with the exiting 5-2 compressors. The proposed circuits improve the delay, PDP, and transistor count compared to the existing design. According to the simulation result, the first and second proposed designs have decreased the PDP value by about 51% and 66%, respectively than the previous work.

Keywords

Main Subjects


[1] A. Amirany and R. Rajaei, “Fully nonvolatile and low power full adder based on spin transfer torque magnetic tunnel junction with spin-hall effect assistance”, IEEE Transactions on Magnetics, vol. 54, no. 12, pp. 1-7, 2018.
[2[ F. Sharifi; A. H. Hosseini; M. Nouraei. “Design of a CNFET-based Quaternary Full Adder”, TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, vol. 54, no. 2, pp. 183-192, 2024, (in persian).
[3] R. Abbasi, and V. Jamshidi, “A Non-volatile, Low-Power, and Fast NCFET-based Flip-Flop with Simultaneous Backup Capability for Non-volatile Computing”, TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, vol. 54, no. 1, pp.35-43, 2024.
[4] N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, et al., “Leakage current: Moore's law meets static power”, Computer, vol. 36, no. 12, pp. 68-75, 2003.
[5] F. Razi, M. H. Moaiyeri, R. Rajaei, and S. Mohammadi, “A variation-aware ternary spin-Hall assisted STT-RAM based on hybrid MTJ/GAA-CNTFET logic”, IEEE Transactions on Nanotechnology, vol. 18, pp. 598-605, 2019.
[6] A. Amirany and R. Rajaei, “Nonvolatile, spin-based, and low-power inexact full adder circuits for computing-in-memory image processing”, Spin, vol. 9, no. 03, p. 1950013, 2019.
[7] A. Zarei and F. Safaei, “Power and area-efficient design of VCMA-MRAM based full-adder using approximate computing for IoT applications”, Microelectronics journal, vol. 82, pp. 62-70, 2018.
[8] H. Cai, Y. Wang, L. A. Naviner, Z. Wang, and W. Zhao, “Approximate computing in MOS/spintronic non-volatile full-adder”, in IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), pp. 203-208.
[9] K. C. Chun, H. Zhao, J. D. Harms, T.-H. Kim, J.-P. Wang, and C. H. Kim, “A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory”, IEEE journal of solid-state circuits, vol. 48, no. 2, pp. 598-610, 2012.
[10] H. Thapliyal, A. Mohammad, S. D. Kumar, and F. Sharifi, “Energy-efficient magnetic 4-2 compressor”, Microelectronics journal, vol. 67, pp. 1-9, 2017.
[11] N. Sakimura, T. Sugibayashi, R. Nebashi, and N. Kasai, “Nonvolatile magnetic flip-flop for standby-power-free SoCs”, IEEE Journal of Solid-State Circuits, vol. 44, no. 8, pp. 2244-2250, 2009.
[12] S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, “Computing in memory with spin-transfer torque magnetic RAM”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 470-483, 2017.
[13] J. Sun, X. Zhao, and Y. Wang, “A Three Input Look-Up-Table Design Based on Memristor-CMOS”, in Bio-inspired Computing: Theories and Applications: 13th International Conference, BIC-TA November 2–4, 2018, Beijing, China, pp. 275-286.
[14] D. Cho, K. Kim, and C. Yoo, “A non-volatile ternary content-addressable memory cell for low-power and variation-toleration operation”, IEEE transactions on magnetics, vol. 54, no.2, pp. 1-3, 2017.
[15] A. A. Javadi, M. Morsali, and M. H. Moaiyeri, “Magnetic nonvolatile flip-flops with spin-Hall assistance for power gating in ternary systems”, Journal of Computational Electronics, vol. 19, no.3, pp. 1175-1186, 2020.
[16] C.-W. Tung and S.-H. Huang, “Low-power high-accuracy approximate multiplier using approximate high-order compressors”, in 2nd International Conference on Communication Engineering and Technology (ICCET) 2019, Nagoya, Japan, pp. 163-167.
[17] D. Balobas and N. Konofaos, “Low‐power high‐performance CMOS 5‐2 compressor with 58 transistors”, Electronics Letters, vol. 54, no.5, pp. 278-280, 2018.
[18] R. K. Senapati and J. Ravindra, “Low-power near-explicit 5:2 compressor for superior performance multipliers”, International Journal of Engineering, vol. 11, no. 4, pp. 529-545, 2018.
[19] S. Sowmiya, K. Stella, and V. Senthilkumar, “Design and analysis of 4-2 compressor for arithmetic application”, Asian Journal of Applied Science and Technology (AJAST), vol. 1, no. 1, pp. 106-109, 2017.
[20] M. Ahmadinejad and M. H. Moaiyeri, “Energy-efficient magnetic 5: 2 compressors based on SHE-assisted hybrid MTJ/FinFET logic”, Journal of Computational Electronics, vol. 19, no. 1, pp. 206-221, 2020.
[21] E. Deng, Y. Zhang, J.-O. Klein, D. Ravelsona, C. Chappert, and W. Zhao, “Low power magnetic full-adder based on spin transfer torque MRAM”, IEEE transactions on magnetics, vol. 49, no. 9, pp. 4982-4987, 2013.
[22] F. Ren and D. Markovic, “True energy-performance analysis of the MTJ-based logic-in-memory architecture (1-bit full adder)”, IEEE transactions on electron devices, vol. 57, no. 5, pp. 1023-1028. 2010.
[23] F. Sharifi, Z. Saifullah, and A.-H. Badawy, “Design of adiabatic MTJ-CMOS hybrid circuits”, in IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) 2017, Boston, MA, USA, pp. 715-718.
[24] R. Zand, A. Roohi, and R. F. DeMara, “Energy-efficient and process-variation-resilient write circuit schemes for spin hall effect MRAM device”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2394-2401, 2017.
[25] W. Kang, L. Zhang, J.-O. Klein, Y. Zhang, D. Ravelosona, and W. Zhao, “Reconfigurable codesign of STT-MRAM under process variations in deeply scaled technology”, IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 1769-1777, 2015.
[26] A. Amirany and R. Rajaei, “Spin-based fully nonvolatile full-adder circuit for computing in memory”, Spin, vol. 9, no. 01, p. 1950007, 2018.
[27] Y. Gang, W. Zhao, J.-O. Klein, C. Chappert, and P. Mazoyer, “A high-reliability, low-power magnetic full adder”, IEEE Transactions on Magnetics, vol. 47, no. 11, pp. 4611-4616, 2011.
[28] H. Thapliyal, F. Sharifi, and S. D. Kumar, “Energy-efficient design of hybrid MTJ/CMOS and MTJ/nanoelectronics circuits”, IEEE Transactions on Magnetics, vol. 54, no. 7,pp. 1-8, 2018.
[29] R. Rajaei and S. B. Mamaghani, “Ultra-low power, highly reliable, and nonvolatile hybrid MTJ/CMOS based full-adder for future VLSI design”, IEEE Transactions on device and materials reliability, vol. 17, no. 1, pp. 213-220, 2016.
[30] C-H. Chang, J. Gu, and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 10, pp. 1985. 2004.
[31] S. Agarwal, G. Harish, S. Balamurugan, and R. Marimuthu, “Design of high speed 5: 2 and 7: 2 compressor using nanomagnetic logic”, in VLSI Design and Test: 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, pp. 49-60.
[32] J. Kim, A. Chen, B. Behin-Aein, S. Kumar, J.-P. Wang, and C. H. Kim, “A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies”, in IEEE custom integrated circuits conference (CICC), 2015, San Jose, CA, USA, pp. 1-4.
[33] Bagherizadeh, M., Moaiyeri, M. H., & Eshghi, M. A “high-performance 5-to-2 compressor cell based on carbon nanotube FETs”, International Journal of Electronics, vol.106, no. 6, pp. 912-927, 2019.
[34] Chu, Kan M., and David L. Pulfrey. “A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic”, IEEE Journal of Solid-State Circuits 22, no. 4, pp 528-532, 1987.