Low Power Bulk-Driven Time-Domain Comparator with High Voltage-to-Time Gain

Document Type : Original Article

Authors

Department of Electrical Engineering, Mashhad Branch, Islamic Azad University, Mashhad, Iran.

Abstract

This paper presents a time-domain comparator with low supply voltage and low power consumption for using in circuits that comparator’s input common-mode voltages swing is 0 to half supply voltage. To design the time-domain comparator, a delay element with a very high delay-voltage gain is proposed. The purpose of designing this comparator is to achieve high delay-voltage gain, which leads to an increase in the accuracy of the comparator, as well as a significant reduction in power consumption and occupied area compared to conventional time-domain comparators. This time-domain comparator utilizes subthreshold concept and also uses the bulk-voltage of transistor as a comparator input. The proposed comparator is simulated in 0.18µm TSMC technology at 1V supply voltage, which according to the intended application, the supply voltage can be reduced to about 0.4V. The simulation results show that with supply voltage of 1V the proposed comparator consumes 250nW at the clock frequency of 2.5MHz. The figure of merit of 0.1µW/MHz indicates the high performance of the proposed comparator. Based on the Monte Carlo simulation, the offset voltage of this comparator is obtained 2.8mV.

Keywords

References

[1]   A. Gupta, A. Singh, A. Agarwal, "A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique", AEU-International Journal of Electronics and Communications, vol. 134, p. 153682, 2021.
[2]   C. W. Casañas, G. A. Souza, O. Saotome, R. L. Moreno, "Low power current comparator circuit using a cascode transistor structure for bias generation", Microelectronics Journal, p. 105359, 2022.
[3]   O. Aiello, P. Crovetti, P. Toledo, and M. Alioto, "Rail-to-rail dynamic voltage comparator scalable down to pW-range power and 0.15-V supply", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, pp. 2675-2679, 2021.
[4]   مهدی حسین‌نژاد، حسین شمسی, «طراحی و شبیه‌سازی مبدل آنالوگ به دیجیتال لوله‌ای مبتنی بر مقایسه‌گر ولتاژ پایین»، مجله مهندسی برق دانشگاه تبریز، جلد 46، شماره 1، صفحات 87-98، 1395.
 [5]  V. Savani, N. Devashrayee, "Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator", Analog Integrated Circuits and Signal Processing, vol. 93, pp. 287-298, 2017.
[6]   A. Khorami, R. Saeidi, M. Sachdev, M. Sharifkhani, "A low-power dynamic comparator for low-offset applications", Integration, vol. 69, pp. 23-30, 2019.
[7]   H. S. Bindra, C. E. Lokin, D. Schinkel, A.-J. Annema, B. Nauta, "A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise", IEEE journal of solid-state circuits, vol. 53, pp. 1902-1912, 2018.
[8]   P. Harikumar, J. J. Wikner, "A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer", Integration, vol. 50, pp. 28-38, 2015.
[9]   S. Babayan-Mashhadi, R. Lotfi, "Analysis and design of a low-voltage low-power double-tail comparator", IEEE transactions on very large scale integration (vlsi) systems, vol. 22, pp. 343-352, 2013.
[10] S.-K. Lee, S.-J. Park, H.-J. Park, J.-Y. Sim, "A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface", IEEE Journal of Solid-State Circuits, vol. 46, pp. 651-659, 2011.
[11]  سعید نقوی, سید ادیب ابریشمی فر، «یک مقایسه کننده قفل‌شده تمام تفاضلی مجهز به روش نوین حذف آفست»، مجله مهندسی برق دانشگاه تبریز, جلد 48، شماره 4، صفحات 1831-1842، 1397.
[12] A. Agnes, E. Bonizzoni, P. Malcovati, F. Maloberti, "A 9.4-ENOB 1V 3.8 μW 100kS/s SAR ADC with time-domain comparator", in 2008 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, 2008, pp. 246-610.
[13] S.-E. Hsieh, C.-C. Kao, C.-C. Hsieh, "A 0.5-V 12-bit SAR ADC using adaptive time-domain comparator with noise optimization", IEEE Journal of Solid-State Circuits, vol. 53, pp. 2763-2771, 2018.
[14] X. Yang, Y. Zhou, M. Zhao, Z. Huang, L. Deng, X. Wu, "A 0.9 v 12-bit 200-ks/s 1.07 µw sar adc with ladder-based reconfigurable time-domain comparator", 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 105-108, 2014.
[15] R. Sanati, F. Khatib, M. J. Sarraf,R. K. Moghaddam, "Low power time-domain rail-to-rail comparator with a new delay element for ADC applications", Integration, vol. 77, pp. 89-95, 2021.
[16] R. Fiorelli, M. Delgado-Restituto, Á. Rodríguez-Vázquez, "Offset-calibration with time-domain comparators using inversion-mode varactors", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, pp. 47-51, 2019.
[17] X. Zhong, B. Wang, A. Bermak, "A reconfigurable time-domain comparator for multi-sensing applications", 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 349-352, 2015.
[18] A. H. Hassan, H. Mostafa, K. N. Salama, A. M. Soliman, "A low-power time-domain comparator for iot applications", 2018 IEEE 61th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1142-1145,2018.
[19] S. Rout, S. Babayan-Mashhadi, W. A. Serdijn, "A subthreshold source-coupled logic based time-domain comparator for SAR ADC based cardiac front-ends", 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 17-20, 2019.
[20] M. Kumngern, F. Khateb, T. Kulej, "Bulk-driven fully balanced second-generation current conveyor in 0.18 µm CMOS", AEU-International Journal of Electronics and Communications, vol. 104, pp. 66-75, 2019.
[21] A. Nejati, S. Radfar, P. Amiri, M. H. Maghami, "A bulk-driven differential CMOS schmitt trigger with adjustable hysteresis for ultra-low-voltage operation", Microelectronics Journal, vol. 114, p. 105129, 2021.
[22] T. Kulej, F. Khateb, "A compact 0.3-V class AB bulk-driven OTA", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, pp. 224-232, 2019.
[23] L. Nagy, D. Arbet, M. Kovac, M. Potocny, M. Sovcik, V. Stopjakova, "Dynamic Properties Of Ultra Low-Voltage Rail-to-Rail Comparator Designed In 130 nm CMOS Technology", 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 1-4, 2020.
[24] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, "A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure", IEEE Journal of Solid-State Circuits, vol. 45, pp. 731-740, 2010.
[25] L. Xie, G. Wen, J. Liu, Y. Wang, "Energy-efficient hybrid capacitor switching scheme for SAR ADC", Electronics Letters, vol. 50, pp. 22-23, 2014.
[26] C. Yuan, Y. Lam, "Low-energy and area-efficient tri-level switching scheme for SAR ADC", Electronics letters, vol. 48, pp. 482-483, 2012.
[27] E. W. NH, D. Harris, A. Banerjee, "CMOS VLSI design: A circuit and system perspective", Addison-Wesley, Boston, 2005.
[28] L. Nagy, V. Stopjakova, D. Arbet, M. Potocny, M. Kovac, "An ultra low-voltage rail-to-rail comparator for on-chip energy harvesters", AEU-International Journal of Electronics and Communications, vol. 108, pp. 10-18, 2019.
TABRIZ JOURNAL OF ELECTRICAL ENGINEERING
Volume 51, Issue 4 - Serial Number 98
December 2021
Pages 393-401

Files

Share

How to cite

Statistics