Approximate Fault Simulation for Quick Evaluation of Test Patterns in Digital Circuit Testing

Document Type : Original Article

Authors

Department of Computer Engineering and Information Technology, Razi University, Kermanshah, Iran

Abstract

Simulation-based test pattern generation methods are an interesting alternative to deterministic methods because of lower time complexity. In these methods, test patterns are evaluated and those with higher efficiency are selected. Traditionally, test pattern selection is based on fault coverage, which is an accurate merit indicator, but its calculation is time-consuming. Instead of fault coverage, approximate indicators can be used to assess efficiency of test patterns. In this paper, an approximate indicator called APXD is proposed, which is more efficient than existing approximate methods. Our experimental results show that APXD indicator has a strong correlation with fault coverage. In addition, APXD simulation is 1900x, 63x, and 56x faster than serial, sampling, and parallel fault simulation, respectively. Exploiting APXD indicator instead of fault coverage, in a pruning-based test generation method, leads to about 700x, 24.2x, and 18.4x speedup, respectively compared to pruning based methods that use serial, sampling, or parallel fault simulation for test pattern evaluation, at fault coverage of 80%. Speedup at fault coverage of 95% is about 111.3x, 11.1, and 3.6x, respectively. While, the use of APXD indicator instead of fault coverage increases the number of test vectors by 2% at most, confirming the efficiency of APXD indicator compared with probabilistic and statistical approximate indicators.

Keywords

References

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TABRIZ JOURNAL OF ELECTRICAL ENGINEERING
Volume 51, Issue 3 - Serial Number 97
November 2021
Pages 347-357

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