Fault Tolerant ALU Designing based on New Implementation of Berger Code

Towhidy Gol, A.; Omidi, R.; Mohammadi, K.

Fault Tolerant ALU Designing based on New Implementation of Berger Code

Document Type : Original Article

Authors

¹ School of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran

² Faculty of Engineering, University of Zanjan, Zanjan, Iran

³ School of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

Abstract

ALU is one of the most sensitive units of a processor, which most of the instructions of a processor are executed by this section. In most of the Architecture methods for mitigation of fault such as temporal redundancy, it is necessary to detect the errors first. Hardware overhead of test circuits is one of the most important disadvantages for testing small circuits which makes designers to use unusual methods in the design of small circuits. In this Article, a new implementation method for Berger code has been used to detect the error and compared with the previous method that is based on the Berger code. In the proposed method, the current mode circuits are employed to reduce the cost of the Berger code implementation. This circuit has higher speed and less hardware complexity than conventional implementations of Berger code. According to the result of this article, the Power of current mode Berger has been reduced at a rate of 51%, and the area of current mode Berger has been reduced at a rate of 74.3% and also the total cost of the Berger circuit (Power*Delay*Area) has been reduced at a rate of 91%.

Keywords

References

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