قابلیت اطمینان مدارهای دیجیتال با استفاده از گراف‌های سیگنال گذر احتمالاتی

نوع مقاله : علمی-پژوهشی

نویسندگان

1 گروه پژوهشی فناوری اطلاعات و ارتباطات - پژوهشگاه نیرو

2 دانشکده مهندسی - دانشگاه فردوسی مشهد

چکیده

کوچک‌شدن ابعاد ترانزیستورها سبب افزایش قابلیت‌های متعدد مدارهای دیجیتال شده ولی آسیب‌پذیری آنها را در برابر خطاهای گذرا بیشتر کرده‌است. بنابراین تعیین نقاط حساس مدارهای دیجیتال در نقاط مختلف مدار از موارد ضروری در طراحی مدارهای دیجیتال به‌ویژه در فناوری‌های جدید چند نانومتری می‌باشد. از سوی دیگر افزایش تعداد گیت‌های مدارهای دیجیتال و تنوع خطاهای گذرا در آنها همراه با نحوه انتشار خطا در مدار، موجب می‌شود تا برآورد آسیب‌پذیری در برابر خطاهای گذرا بسیار پیچیده باشد. علاوه‌بر دقت محاسبات، موضوعاتی از قبیل مقیاس‌پذیری روش، پیچیدگی محاسباتی، زمان محاسبه و حافظه مصرفی نیز باید در نظر گرفته شوند. در این مقاله، ابتدا مفهوم گراف‌های گذر سیگنال احتمالاتی معرفی می‌شود و سپس روشی نوین برای تحلیل آن‌ها پیشنهاد می‌شود که ضمن حفظ دقت، از سرعت محاسبه و مقیاس‌پذیری بالایی برخوردار است. تحلیل احتمالاتی مسیرهای بازهمگرا1،  استفاده از روش تکرار نقطه ثابت و به‌کارگیری ماتریس‌های تُنُک2 از ویژگی‌های خاص روش پیشنهادی می‌باشد. با استفاده از روش پیشنهادی، قابلیت اطمینان مدارهای دارای فیدبک و مدارهای ترتیبی نیز مورد ارزیابی قرار می‌گیرد. در نتیجه شبیه‌سازی‌ها، پیچیدگی محاسباتی روش پیشنهادی برای تحلیل مداری با N گره در هر دو حالت ترکیبی و ترتیبی به‌ترتیب برابر O(N0.85) و O(N0.99) می‌باشد.

کلیدواژه‌ها

عنوان مقاله [English]

Reliability Evaluation of Digital Circuits Using Probabilistic Signal Flow Graphs

نویسندگان [English]

  • V. Hamiyati Vaghef 1
  • A. Peiravi 2
1 Department of ICT, Niroo Research Institute, Tehran, Iran
2 Faculty of Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
چکیده [English]

Although reducing the size of transistors increased their capabilities considerably, but also resulted in more susceptibility to transient errors. Thus, detecting the sensitive nodes of digital circuits is essential for designing digital circuits at few nanometers. On the other hand, increasing the number of logic gates, transient error types and several error propagation mechanisms in digital circuits, results in considerable complexity in reliability evaluation. Thus, scalability, computational complexity, runtime, accuracy and memory consumption should be taken into account for such evaluation. In this paper, using the concept of the probabilistic signal flow graphs, a new approach is proposed to evaluate the reliability of digital circuits which demonstrates good accuracy, runtime and high level of scalability. Probabilistic evaluation of re-convergent paths, using fixed point theorem and using the sparsity of matrices are features of the proposed approach. Using the proposed approach, the reliability of circuits with feedback and sequential circuits is also evaluated. Simulation results show that the computational complexity of the proposed approach for a combinational and sequential circuit with N nodes is O(N0.85) and O(N0.99) respectively.

کلیدواژه‌ها [English]

  • Susceptibility of digital circuits
  • transient faults
  • probabilistic graph
  • scalable approach
  • sparse matrices
  • combinational and sequential circuits

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