Operational Trans-conductance Amplifier by Current Recycling Branches for Ultra Low Power Application


Faculty of Engineering, University of Zanjan, Zanjan, Iran


In this paper an ultra-low power two stage improved operational trans_conductance amplifier based on folded cascode is designed. The proposed operational trans_conductance amplifier operates in weak inversion region.  The use of two folded branches in the signal amplification path for the first stage and the new feed_forward compensation path with low bias current on the second stage in this proposed amplifier increases the DC gain, unity gain frequency, slew rate and decreases the input referred noise. The simulation results in a TSMC 0.18µm CMOS technology it shows that the proposed operational trans_conductance amplifier has unity gain bandwidth of 117 KHz, and consumes 195 nW power from a 0.6 V supply voltage with DC gain of 101.4 dB.


[1] R. Assaad, and J. Silva-Martinez, "Enhancing general performance of folded cascode amplifier by recycling current", IET Electronics Letters, vol. 43, No. 23, pp. 1243-1244, Nov. 2007.
[2] W. Bai, Z. Zhu, "A 0.5-V power-efficient low-noise CMOS instrumentation amplifier for wireless biosensor", Microelectronics J, vol. 51, pp. 30–37, May 2016.
[3] R.S. Assaad, J. Silva-Martinez, "The recycling folded cascode: A general enhancement of the folded cascode amplifier", IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, Sep. 2009.
[4] P. Wu, V. Cheung, H. Luong, "A 1-V 100-MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture", IEEE J. Solid State Circuits, vol. 42, no. 4, pp. 730-738, Mar. 2007.
[5] Z. Yan, P. Mak, R.  Martins, "Double recycling technique for folded-cascode OTA", Analog Integr Circ Sig Process, vol. 71, pp. 137–141, Apr. 2012.
[6] X. Zhao, H. Fang, J. Xu, "Phase-margin enhancement technique for recycling folded cascode amplifier", Analog Integr Circ Sig Process, vol. 74,pp. 479-483, Feb. 2013.
[7] M. Yavari, T. Moosazadeh, "A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits", Analog Integr Circ Sig Process, vol. 79, pp. 589–598, Jun. 2014.
[8] T. Aghaee, S. Biabanifard,A. Golmak, "Gain boosting of recycling folded cascode OTA using positive feedback and introducing new input path", Analog Integr Circ Sig Process, vol. 90, pp. 237-246, Jan 2017.
[9] A. Sarkar,S. Panda, "Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique", Microsyst Technol, vol. 23,pp. 4255-4262, Sep. 2017.
[10] M. Akbari, M. Nazari, L. Sharifi, O. Hashemipour, "Improving power efficiency of a two-stage operational amplifier for biomedical applications", Analog Integr Circ Sig Process, vol. 84, pp. 173-183,  Aug. 2015.
[11] خلیل منفردی، یوسف بلقیس‌آذر، « تقویت‌کننده کسکود تمام تفاضلی بازیابی تاشده بهبودیافته ولتاژ و توان پایین»، مجله مهندسی برق دانشگاه تبریز، دوره 48 ، شماره 1، صفحات 327-334، بهار 1397.
[12] A. D. Sundararajan, S. M. Rezaul Hasan, "Quadruply Split Cross-Driven Doubly Recycled-Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 6, pp. 543-547, Jun. 2016.
[13] C. C. Enz, F. Krummenacher, and E. A.Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low voltage and low-current applications", Analog Integr. Circuits Signal Process., vol. 8, pp. 83–114, Jul. 1995.
[14] Chan, P. K., & Chen, Y. C, “Gain-enhanced feedforward path compensation technique for pole-zero cancellation at heavy capacitive loads”, IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing,vol. 50,pp. 933–941, Dec. 2003.
[15] D. Johns and K. Martin, “Analog Integrated Circuit Design”, NewYork: Wiley, 1997.
[16] Z. Qin, A. Tanaka, N. Takaya, H. Yoshizawa, "0.5-V70-nW Rail-to-Rail Operational Amplifier Using a Cross-coupled Output Stage", IEEE Transactions on Circuits and Systems II, vol. 55, no. 3, pp. 1009-1013, Mar. 2016.
[17] A.N. Ragheb, H.W. Kim, "Ultra-low power OTA based on bias recycling and subthreshold operation with phase margin enhancement", Microelectronics Journal, vol. 60, pp. 94-101, Feb. 2017.
[18] L. H. C. Ferreira, S. R. Sonkusale, "A 60-dB gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process", IEEE Trans. Circuits Syst. I, vol. 61, no. 6, pp. 1609-1617, Jul. 2014.
[19] A. D. Grasso, D. Marano, G. Palumbo, S. Pennisi, "Design methodology of subthreshold three-stage CMOS OTAs suitable for ultra-low-power low-area and high driving capability", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 62, no. 6, pp. 1453-1462, Apr. 2015.