Design and Simulation of a 8-Channel, Low-Power, and Small Chip-Area Neural Interfacing Chip

Document Type : Original Article

Authors

1 Faculty of Electrical Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran

2 Electrical Engineering Department, K. N. Toosi University of Technology, Tehran, Iran

Abstract

This article reports on the design of a 8-channel neural recording amplifier and stimulation back-end in TSMC 0.18µm technology which can do the recording and stimulating simultaneously. The design of proposed neural amplifier is based on indirect negative feedback and provides tunable lower cutoff frequency, and digitally-programmable upper cutoff frequency and voltage gain. Moreover, the proposed circuit employs attenuators in the same feedback loop in order to further reduce the silicon area consumed by the capacitors and at the same time to increase the input impedance of the circuit. The 8-channel designed circuit consumes 0.27mm2 of chip area and operated with a supply voltage of 1.8V, power consumption of each channel is 27µW with the THD of -50dB@1kHz and output voltage swing of 0.95Vpp < /sub>. The designed stimulation bak-end circuit, in addition to traditional rectangular pulse shapes, can generates biphasic stimulation pulses with exponential shapes, whose time constants are digitally programmable. A class-B second generation current conveyor is designed to be used for delivering stimulation current pulses of up to ±96µA to the target tissue and a charge pump block is in charge of the generating supply voltages of ±3.3V. The circuit consumes 0.043mm2 of silicon area for each channel (excluding charge pumps). Simulation results indicate that the stimuli generator meets expected requirements with the maximum power consumption of 1.2mW when connected to electrode-tissue impedance of as high as 25kΩ.

Keywords

References

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