[1] سعید پارسا و محمد حمزهیی، "کاشیبندی حلقههای تودرتو با در نظر گرفتن محلیت دادهها بهمنظور اجرای موازی بر روی پردازندههای چندهستهای"، مجله مهندسی برق دانشگاه تبریز، جلد 54، شماره 3، صفحات 17-26، پاییز 94.
[2] سعیده نبیپور، جواد جاویدان و غلامرضا زارع فتین، " طراحی یک دیکدر BCH بهینه جهت افزایش اطمینان در ذخیرهسازی اطلاعات و تصحیح خطا در حافظههای فلش"، مجله مهندسی برق دانشگاه تبریز، جلد ۴۶، صفحات 319-331، شماره ۳، پائیز 95.
[3] M.K. Qureshi, D-H Kim, S. Khan, P.J. Nair and O. Mutlu, “AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems”, in Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), pp. 1-11, 2015.
[4] S. Ovshinsky, “Reversible Electrical Switching Phenomena in Disordered Structures,” Physical Review Letter, vol. 21, no. 20, pp. 1450–1453, 1968.
[5] M. K. Qureshi, S. Gurumurthi and B. Rajendran, Phase Change Memory: From Devices to Systems, Morgan & Claypool Publishers, 2011.
[6] A.L. Lacaita and A. Redaelli, “The race of phase change memories to nanoscale storage and applications”, Microelectronic Engineering, vol. 109, pp. 351-356, 2013.
[7] Y. Choi, I. Song, M.-H. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo, J. Shin, Y. Rho, C. Lee, M. G. Kang, J. Lee, Y. Kwon, S. Kim, J. Kim, Y.-J. Lee, Q. Wang, S. Cha, S. Ahn, H. Horii, J. Lee, K. Kim, H. Joo, K. Lee, Y.-T. Lee, J. Yoo and G. Jeong, “A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth,” in Proceedings of IEEE International Solid-State Circuits Conference, pp. 46–48, 2012.
[8] M. Han, Y. Han, S.W. Kim, H. Lee and I. Park, “Content-Aware Bit Shuffling for Maximizing PCM Endurance”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 22, no. 3, Article no. 48, 2017.
[9] N. Papandreou, H. Pozidis, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam and E. Eleftheriou, “Programming algorithms for multilevel phasechange memory,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 329–332, 2011.
[10] O. Zilberberg, S. Weiss and S. Toledo, “Phase-Change Memory: An Architectural Perspective,” ACM Computing Surveys, vol. 45, no. 3, Article no. 29, 2013.
[11] S. C. Woo, M. Ohara, E. Torrie, J. P. Singh and A. Gupta, “The SPLASH-2 programs: characterization and methodological considerations,” ACM SIGARCH Computer Architecture News, vol. 23, no. 2, pp. 24–36, 1995.
[12] C. Bienia, S. Kumar, J. P. Singh and K. Li, “The PARSEC benchmark suite: characterization and architectural implications,” in Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 72-81, 2008.
[13] R. Ubal, B. Jang, P. Mistry, D. Schaa and D. Kaeli, “Multi2Sim: A Simulation Framework for CPU-GPU Computing,” in Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, pp. 335-344, 2012.
[14] F. Bedeschi, R. Fackenthal, C. Resta, E. M. Donze, M. Jagasivamani, E. C. Buda, F. Pellizzer, D. W. Chow, A. Cabrini, G. M. A. Calvi, R. Faravelli, A. Fantini, G. Torelli, D. Mills, R. Gastaldi and G. Casagrande, “A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage,” IEEE Journal on Solid-State Circuits, vol. 44, no. 1, pp. 217–227, 2009.
[15] J. Wang, X. Dong, G. Sun, D. Niu and Y. Xie, “Energy-efficient multi-level cell phase-change memory system with data encoding,” in Proceedings of IEEE 29th International Conference on Computer Design, pp. 175–182, 2011.
[16] F. Bedeschi, C. Resta, O. Khouri, E. Buda, L. Costa, M. Ferraro, F. Pellizzer, F. Ottogalli, A. Pirovano, M. Tosi, R. Bez, R. Gastaldi and G. Casagrande, “An 8Mb demonstrator for high-density 1.8V Phase-Change Memories,” in Proceedings of Symposium on VLSI Circuits, pp. 442-445, 2004.