K. Kim, “Future memory technology: challenges and opportunities,” Proceedings of International Symposium on VLSI Technology, Systems and Applications, pp. 5-9, 2008.
 K. Pangai, “90 nm Multi-level-cell flash memory technology,” IEEE International Symposium on Semiconductor Manufacturing, pp. 197-199, 2010.
 S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, Prentice- Hall Inc, 2004.
 J. Cho and W. Sung, “Strength-reduced parallel chien search architecture for strong BCH codes,” IEEE Transaction on Circuits and Systems, vol. 55, no. 5, pp. 427-431, 2008.
 Y. M. Lin, C. H. Yang, C. H. Hsu, H. C. Chang and C. Y. Lee, “A MPCN-based parallel architecture in BCH decoders for NAND flash memory devices,” IEEE Transaction on Circuits and Systems, vol. 58, no. 10, pp. 682-686, 2011.
 H. Yoo, Y. Lee and I. C, Park, “7.3 Gb/s universal BCH encoder and decoder for SSD controllers,” Design Automation Conference (ASP-DAC), pp. 37-38, 2014.
 Y. Lee, H. Yoo, I. Yoo and I. C. Park, “High-throughput and low-complexity BCH decoding architecture for solid-state drives,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1183–1187, 2014.
 M. Yin, M. Wie and B. Yi, “Optimized algorithm for binary BCH codes,” Circuits and Systems (ISCAS) IEEE Internationa Symposium, pp. 1552-1555, 2013.
 D. V. Sarwate and R. S. Shanbhag, “High-speed architecture for BCH decoders,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 5, pp. 641–655, 2001.
 H. Choi, W. Liu and W. Sung, “VLSI implementation of BCH error correction for multilevel cell NAND flash memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 843–847, 2010.
 T. Chen, Y. Hsiao and Y. Hsing, “An adaptive-rate error correction scheme for NAND flash memory,” 27th IEEE VLSI Test Symposium, pp. 53-58, 2009.
 C. Chu, Y. Lin, C. Yang and H. Chang, “A fully parallel BCH codec with double error correcting capability for NOR flash applications,” in IEEE International Conference ofAcoustics, Speech, and Signal Processing, pp. 1605–1608, 2012.
 X. Wang, P. Liyang, W. Dong and H. Chaohong, “A high-speed two cell BCH decoder for error correcting in mlc NOR flash memories,” IEEE Transactions on Circuits and Systems, vol. 56, no. 11, pp. 865 – 869, 2009.
 V. Mahadevaswamy, S. Sunitha and BN. Shobha, “Implementation of fault tolerant method using BCH code on FPGA,” International Journal of Soft Computing and Engineering (IJSCE), vol. 2, no. 4, pp. 2231-2307, 2012.
 Y. Jiang, A Practical Guide to Error-Control Coding Using MATLAB, Artech House,2010.
 F. Sun, S. Devarajan, K. Rose and T. Zhang, “Design of on-chip error correction systems for multilevel NOR and NAND flash memories,” IET Circuits, Devices and Systems, vol. 1, no. 3, pp. 241-249, 2007.
 Y. Chen and K.K. Parhi, “Area efficient syndrome calculation for strong BCH decoding,” Electronics Letters, vol. 47, no. 2, pp. 107-108, 2011.
 W. Liu, J. Rho and W. Sung, “Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories,” IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 303-308, 2006.
 L. Song, M. Yu and M. S. Shaffer, “10- and 40-Gb/s Forward error correction devices for optical communications,” IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1565-1573, 2002.
 H. Lee, “High-speed VLSI architecture for parallel reed-solomon decoder,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 2, pp. 288–294, 2003.
 M. Edoardo, VLSI Architecture for Computations in Galois Fields, Ph.D. Thesis, University of Linkoping, Sweden, WA, 2006.
 C. Paar, “Optimized arithmetic for reed-solomon encoders,” in Proceedings of IEEE International Symposium Information Theory, 250-250, 1997.
 M. Potkonjak, M. Srivastava and A. Chandrakasan, “Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination,” IEEE Transactions on Computer-Aided Design, vol. 15, pp. 151-165, 1996.
 J. Hennessy and D. Patterson, Computer Architecture a Quantitative Approach, Morgan Kaufmann Publishers, 2007.
 Micron, Technical Note: Parallel NOR Flash Embedded Memory.
 Y. M. Lin, H. C. Chang and C. Y. Lee, “Improve high code-rate soft BCH decoder architecure with one extra error compensation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 11, pp. 2160–2164, 2013.