طراحی یک دیکدر BCH بهینه جهت افزایش اطمینان در ذخیره سازی اطلاعات و تصحیح خطا در حافظه های فلش

نویسندگان

دانشگاه محقق اردبیلی

چکیده

چکیده: کاهش ابعاد ترانزیستورها در نسل جدید حافظه­های فلش و رهسپار شدن آن‌ها به سمت حوزه­­­های طراحی نانومتر منجر به عدم صحت در برنامه­ریزی و پاک کردن اطلاعات در این طراحی­ها شده؛ درنتیجه قابلیت اطمینان در ذخیره­سازی اطلاعات به چالشی مهم در ساختار این نوع حافظه­ها تبدیل شده است. جهت مقابله با چنین چالشی در کنترل‌کننده این نوع از حافظه­ها از کدهای تصحیح خطا­ی BCH استفاده می­شود. دو نکته­ اساسی در فرآیند دیکدینگ کد BCH عبارت‌اند از: میزان تأخیر در فرآیند تصحیح خطا و حجم سخت‌افزاری هر یک از زیر بلوک­ها. در این مقاله جهت افزایش سرعت در فرآیند تصحیح خطا و نیز افزایش راندمان مدار دیکدر، روشی مؤثر مبتنی بر معماری موازی برای زیر بلوک‌های دیکدر BCH و همچنین استفاده از تکنیک خط لوله پیشنهاد شده است. از طرف دیگر راه‌حل پیشنهادی جهت کاهش حجم سخت­افزار بلوک دیکدر BCH، استفاده از الگوریتم اشتراک­گذاری XORها جهت حذف گیت­های تکراری در بلوک Chien search است. دیکدر پیشنهادشده توسط زبان توصیف سخت­افزار VHDL شبیه­سازی و سپس با استفاده از نرم­افزار Xilinx ISE سنتز شده است. نتایج شبیه­سازی­ها نشان می­دهند که الگوریتم پیشنهادی در مقایسه با روش­های مشابه ضمن کاهش زمان فرآیند تصحیح خطا، توانسته است کاهش چشم­گیری در حجم سخت­افزاری بلوک دیکدر BCH داشته باشد.

کلیدواژه‌ها

عنوان مقاله [English]

Design of an Optimum BCH Decoder to Increase the Reliability of Data Storage and Error Correction Mechanism in Flash Memories

چکیده [English]

Abstract: The shrinking of transistor dimensions and migration to nanometer region have increased the data storage errors in new generations of flash memories. Therefore, the reliability of data storage is an important challenge in the structure of these memories. In order to confront with this challenge, BCH error correction codes are utilized in the controller of these memories. There are two important points in the optimization process of a BCH decoder: speeding up the computation and reducing the hardware complexity. To speed up the decoding process, a parallel architecture is utilized for various building blocks. A Pipeline scheme is also adopted in BCH decoder to increase the throughput. To implement this parallel BCH decoder in an area-efficient manner, an iterative matching scheme is proposed to reduce the Chien search hardware complexity by reducing the number of XOR gates through removing the duplicate gates and sharing the remaining ones. The proposed decoder along with BCH encoder have been implemented in VHDL hardware definition language and synthesized in Xilinx ISE. The proposed decoder has been implemented in VHDL hardware definition language and synthesized in Xilinx ISE. The simulation results show that the proposed algorithm could reduce the decoding time and hardware complexity .

کلیدواژه‌ها [English]

  • Keywords: BCH encoder and decoder
  • NAND flash memory
  • reliability
  • error correction code
  • BCH code

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