Reference spur suppression in the Integer-N frequency synthesizers by reducing periodic ripples amplitude on the VCO control voltage

نوع مقاله : علمی-پژوهشی

نویسندگان

Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran.

چکیده

To achieve a low reference spur for an Integer-N frequency synthesizer, a new spur reducing technique was proposed.
To reduce the size of periodic ripples on the VCO control voltage, the low pass filter, and the charge pump were added with a spur reduction system.  By lowering the amplitude of the periodic ripple on the VCO control voltage, we managed to lower the reference spur. The introduced technique removes the necessity to decrease bandwidth and CVO gain reference spur suppressing. To demonstrate the effectiveness of the proposed structure, a 2.06 – 2.22 GHz frequency synthesizer was used and the 180-nm CMOS technology was used for post-layout simulation. The proposed frequency synthesizer represents the reference spur of -85.84 dBc at 20 MHz offset and phase noise of -108dBc/Hz at 200 kHz offset frequency also it is locked after 2.8us while occupied 0.35 mm2 of the chip area.

کلیدواژه‌ها

عنوان مقاله [English]

Reference spur suppression in the Integer-N frequency synthesizers by reducing periodic ripples amplitude on the VCO control voltage

نویسندگان [English]

  • S. Jahangirzadeh
  • A. Amirabadi
  • A. Farrokhi
Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran.
چکیده [English]

To achieve a low reference spur for an Integer-N frequency synthesizer, a new spur reducing technique was proposed.
To reduce the size of periodic ripples on the VCO control voltage, the low pass filter, and the charge pump were added with a spur reduction system.  By lowering the amplitude of the periodic ripple on the VCO control voltage, we managed to lower the reference spur. The introduced technique removes the necessity to decrease bandwidth and CVO gain reference spur suppressing. To demonstrate the effectiveness of the proposed structure, a 2.06 – 2.22 GHz frequency synthesizer was used and the 180-nm CMOS technology was used for post-layout simulation. The proposed frequency synthesizer represents the reference spur of -85.84 dBc at 20 MHz offset and phase noise of -108dBc/Hz at 200 kHz offset frequency also it is locked after 2.8us while occupied 0.35 mm2 of the chip area.

کلیدواژه‌ها [English]

  • Spur suppression
  • reference spur
  • voltage controlled oscillator (VCO)
  • and integer-N frequency synthesizer

مراجع

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مجله مهندسی برق دانشگاه تبریز
دوره 51، شماره 1 - شماره پیاپی 95
اردیبهشت 1400
صفحه 61-69

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