University of Tabriz Tabriz Journal of Electrical Engineering 2008-7799 2025 09 22 Two Stage Body Driven Double Recycling Folded Cascode Operational Transconductance Amplifier with Enhanced Slew Rate and Low Power Consumption Two Stage Body Driven Double Recycling Folded Cascode Operational Transconductance Amplifier with Enhanced Slew Rate and Low Power Consumption 20401 10.22034/tjee.2025.67219.5018 FA Zahra Hashemi Faculty of engineering, University of Zanjan, Zanjan, Iran. Mostafa Yargholi Electrical engineering, Faculty of engineering, University of Zanjan Journal Article 2025 05 10 In this paper, a two stage body driven double recycling folded cascode operational transconductance amplifier with enhanced slew rate and low power consumption is presented. The proposed OTA uses the body driven technique to reduce the power consumption. By combining the double recycling folded casode and body driven structures, this OTA can provide a good performance in the slew rate, CMRR, PSRR, gain, and power parameters. The first stage of the proposed OTA uses four paths to conduct a small signal current, which leads to an obvios increase in transconductance. C_C capacitors are used for frequency compensation. To demonstrate the capabilities and performance of the proposed OTA, post layout simulations with 180nm CMOS technology are performed. The proposed OTA provides a DC gain of 58.5 dB and a phase margin of 71.6 ° at a unity gain frequency of 1.9 KHz for a 200 pF capacitive load. The proposed OTA consumes very low power of 228.7 nW under a 0.9 V supply voltage. Also, the proposed OTA provides higher CMRR and PSRR of 104.5 dB and 78.7 dB, respectively. The proposed OTA is robust to PVT variations. Finally, the FOM performances are improved compared to the previous works. In this paper, a two stage body driven double recycling folded cascode operational transconductance amplifier with enhanced slew rate and low power consumption is presented. The proposed OTA uses the body driven technique to reduce the power consumption. By combining the double recycling folded casode and body driven structures, this OTA can provide a good performance in the slew rate, CMRR, PSRR, gain, and power parameters. The first stage of the proposed OTA uses four paths to conduct a small signal current, which leads to an obvios increase in transconductance. C_C capacitors are used for frequency compensation. To demonstrate the capabilities and performance of the proposed OTA, post layout simulations with 180nm CMOS technology are performed. The proposed OTA provides a DC gain of 58.5 dB and a phase margin of 71.6 ° at a unity gain frequency of 1.9 KHz for a 200 pF capacitive load. The proposed OTA consumes very low power of 228.7 nW under a 0.9 V supply voltage. Also, the proposed OTA provides higher CMRR and PSRR of 104.5 dB and 78.7 dB, respectively. The proposed OTA is robust to PVT variations. Finally, the FOM performances are improved compared to the previous works.