University of Tabriz Tabriz Journal of Electrical Engineering 2008-7799 53 1 2023 03 21 Class-C VCO with Bias Regulator Circuitry for Enhanced Oscillation Swing and Robust Start-Up Class-C VCO with Bias Regulator Circuitry for Enhanced Oscillation Swing and Robust Start-Up 9 23 15797 10.22034/tjee.2023.15797 FA S. Haghdoost M.Sc., Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran,. P. Torkzadeh Assistant Professor, Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran M. Chahardori Assistant Professor, Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran Journal Article 2022 08 09 A novel bias regulator circuitry is introduced for the class-C LC-VCO in this paper, that results in reduced phase noise and amplitude-enhanced and more robustness of start-up than conventional class-C VCO. Setting the bias voltage is such that in the start-up, V_bias to be larger than the threshold voltage and provide a safe start-up, then in the steady state oscillation, it goes less than V_th and increases the maximum oscillation amplitude. In the proposed bias circuitry, by combining the ring oscillator circuit and a rectifier and two inverters in the first stage, a step voltage signal is created which changes from 0 to V_DD and then by applying it to the second stage and the switching operation of the transistors in this stage, the appropriate V_bias is provided. The proposed VCO is implemented in RF 0.18um CMOS process and is simulated by Cadence. Based on the post layout simulations results, the phase noise of the proposed VCO is -121.3dBc/Hz at 1MHz offset frequency from a 5GHz carrier and the power consumption is 2mW, resulting in a FoM of 192.24dBc/Hz. A novel bias regulator circuitry is introduced for the class-C LC-VCO in this paper, that results in reduced phase noise and amplitude-enhanced and more robustness of start-up than conventional class-C VCO. Setting the bias voltage is such that in the start-up, V_bias to be larger than the threshold voltage and provide a safe start-up, then in the steady state oscillation, it goes less than V_th and increases the maximum oscillation amplitude. In the proposed bias circuitry, by combining the ring oscillator circuit and a rectifier and two inverters in the first stage, a step voltage signal is created which changes from 0 to V_DD and then by applying it to the second stage and the switching operation of the transistors in this stage, the appropriate V_bias is provided. The proposed VCO is implemented in RF 0.18um CMOS process and is simulated by Cadence. Based on the post layout simulations results, the phase noise of the proposed VCO is -121.3dBc/Hz at 1MHz offset frequency from a 5GHz carrier and the power consumption is 2mW, resulting in a FoM of 192.24dBc/Hz. https://tjee.tabrizu.ac.ir/article_15797_ddaaea95a5f953675acc6ed2640d6b68.pdf